Storage assignment during high-level synthesis for configurable architectures

Authors:
Wenrui Gong;Gang Wang;R. Kastner
Affiliations:
Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA;Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA;Dept. of Electr. & Comput. Eng., California Univ., Santa Barbara, CA, USA
Venue:
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Year:
2005

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Abstract

Modern, high performance configurable architectures integrate on-chip, distributed block RAM modules to provide ample data storage. Synthesizing applications to these complex systems requires an effective and efficient approach to conduct data partitioning and storage assignment. In this paper, we present a data and iteration space partitioning solution that focuses on minimizing remote memory accesses or, equivalently, maximizing the local computation. Using the same code but different data partitionings, we can achieve faster clock frequencies, without increasing the number of cycles, by simply minimizing global memory accesses. Other optimization techniques like scalar replacement, prefetching and buffer insertion can further minimize remote accesses and lead to average 4.8/spl times/ speedup in overall runtime.