Probability, statistics, and queueing theory with computer science applications
Probability, statistics, and queueing theory with computer science applications
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
The design of a low energy FPGA
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
A survey of design techniques for system-level dynamic power management
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low-power electronics and design
Re-configurable computing in wireless
Proceedings of the 38th annual Design Automation Conference
Exploiting operation level parallelism through dynamically reconfigurable datapaths
Proceedings of the 39th annual Design Automation Conference
Design Methodology of a Low-Energy Reconfigurable Single-Chip DSP System
Journal of VLSI Signal Processing Systems
RaPiD - Reconfigurable Pipelined Datapath
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
Reconfigurable Architectures for General-Purpose Computing
Reconfigurable Architectures for General-Purpose Computing
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
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While performance, area, and power constraints have been thedriving force in designing current communication-enabled embeddedsystems, post-fabrication and run-time adaptability is now required.Two dominant configurable hardware platforms are processorsand FPGAs. However, for compute-intensive applications,neither platform delivers the needed performance at the desiredlow power. The need thus arises for custom, application-specificconfigurable (ASC) hardware.This paper addresses the optimization of ASC hardware. Ourtarget application areas are multimedia and communication wherean incoming packet (task) is processed independently of otherpackets. We innovatively utilize two concepts: external profilingand hardware threading. We utilize an M/M/c queueing model toprofile task arrival patterns and show how profiling guides designdecisions. We introduce the novel concept of hardware threadingwhich allows on-the-fly borrowing of unutilized hardware, thusmaximizing task-level parallelism, to either boost performance orto lower power consumption. We present a scheduling algorithmthat synthesizes a hardware-threaded architecture, and discuss experimentalresults that illustrate adaptability to different workloads,and performance/power trade-offs.