FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
A reconfigurable arithmetic array for multimedia applications
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Static and Dynamic Configurable Systems
IEEE Transactions on Computers
Reconfigurable computing: what, why, and implications for design automation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
An embedded DRAM architecture for large-scale spatial-lattice computations
Proceedings of the 27th annual international symposium on Computer architecture
A decade of reconfigurable computing: a visionary retrospective
Proceedings of the conference on Design, automation and test in Europe
A dynamically reconfigurable hardware-based cipher chip
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Reconfigurable media processing
Parallel Computing - Parallel computing in image and video processing
An FPGA architecture with enhanced datapath functionality
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Pattern Recognition Tool to Detect Reconfigurable Patterns in MPEG4 Video Processing
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Exploiting Content Variation and Perception in Power-Aware 3D Graphics Rendering
PACS '00 Proceedings of the First International Workshop on Power-Aware Computer Systems-Revised Papers
Reconfigurable Computing between Classifications and Metrics - The Approach of Space/Time-Scheduling
FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications
Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Wordlength as an Architectural Parameter for Reconfigurable Computing Devices
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Field-Programmable Custom Computing Machines - A Taxonomy -
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Embedded Reconfigurable Logic Core for DSP Applications
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Metrics for design space exploration of heterogeneous multiprocessor embedded systems
Proceedings of the tenth international symposium on Hardware/software codesign
MICRONEURO '99 Proceedings of the 7th International Conference on Microelectronics for Neural, Fuzzy and Bio-Inspired Systems
The Universal Configurable Block/Machine—An Approach for a Configurable SoC-Architecture
The Journal of Supercomputing
Nanowire-based sublithographic programmable logic arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Hardware Scheduling for Dynamic Adaptability using External Profiling and Hardware Threading
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Task scheduling for heterogeneous reconfigurable computers
SBCCI '04 Proceedings of the 17th symposium on Integrated circuits and system design
Design of programmable interconnect for sublithographic programmable logic arrays
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
IEEE-Compliant IDCT on FPGA-Augmented TriMedia
Journal of VLSI Signal Processing Systems
Nanowire-based programmable architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
IEEE-compliant IDCT on FPGA-augmented TriMedia
Journal of VLSI Signal Processing Systems
Event-oriented computing with reconfigurable platform
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Affinity-Driven System Design Exploration for Heterogeneous Multiprocessor SoC
IEEE Transactions on Computers
Reconfigurable solutions for very-long arithmetic with applications in cryptography
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Proceedings of the 45th annual Design Automation Conference
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Reconfigurable Computing: The Theory and Practice of FPGA-Based Computation
Power scalability in a mesh-connected reconfigurable architecture
ACM Transactions on Embedded Computing Systems (TECS)
Compiling for reconfigurable computing: A survey
ACM Computing Surveys (CSUR)
Evaluating variable-grain logic cells using heterogeneous technology mapping
ARC'07 Proceedings of the 3rd international conference on Reconfigurable computing: architectures, tools and applications
Characterization of Fixed and Reconfigurable Multi-Core Devices for Application Acceleration
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Window memoization: an efficient hardware architecture for high-performance image processing
Journal of Real-Time Image Processing
Dealing with the "itanium effect" (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Design and analysis of adaptive processor
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Reconfigurable Blocks Based on Balanced Ternary
Journal of Signal Processing Systems
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Hi-index | 0.01 |
General-purpose computing devices allow us to (1) customize computation after fabrication and (2) conserve area by reusing expensive active circuitry for different functions in time. We define RP-space, a restricted domain of the general-purpose architectural space focussed on reconfigurable computing architectures. Two dominant features differentiate reconfigurable from special-purpose architectures and account for most of the area overhead associated with RP devices: (1) instructions which tell the device how to behave, and (2) flexible interconnect which supports task dependent dataflow between operations. We can characterize RP-space by the allocation and structure of these resources and compare the efficiencies of architectural points across broad application characteristics. Conventional FPGAs fall at one extreme end of this space and their efficiency ranges over two orders of magnitude across the space of application characteristics. Understanding RP-space and its consequences allows us to pick the best architecture for a task and to search for more robust design points in the space. Our DPGA, a fine- grained computing device which adds small, on-chip instruction memories to FPGAs is one such design point. For typical logic applications and finite- state machines, a DPGA can implement tasks in one-third the area of a traditional FPGA. TSFPGA, a variant of the DPGA which focuses on heavily time-switched interconnect, achieves circuit densities close to the DPGA, while reducing typical physical mapping times from hours to seconds. Rigid, fabrication-time organization of instruction resources significantly narrows the range of efficiency for conventional architectures. To avoid this performance brittleness, we developed MATRIX, the first architecture to defer the binding of instruction resources until run-time, allowing the application to organize resources according to its needs. Our focus MATRIX design point is based on an array of 8-bit ALU and register-file building blocks interconnected via a byte-wide network. With today''s silicon, a single chip MATRIX array can deliver over 10 Gop/s (8-bit ops). On sample image processing tasks, we show that MATRIX yields 10-20x the computational density of conventional processors. Understanding the cost structure of RP-space helps us identify these intermediate architectural points and may provide useful insight more broadly in guiding our continual search for robust and efficient general-purpose computing structures.