Reconfigurable computing: what, why, and implications for design automation
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The Future of Systems Research
Computer
Platform-Based Design and Software Design Methodology for Embedded Systems
IEEE Design & Test
Deep-Submicron Microprocessor Design Issues
IEEE Micro
Instruction-Level Parallelism for Reconfigurable Computing
FPL '98 Proceedings of the 8th International Workshop on Field-Programmable Logic and Applications, From FPGAs to Computing Paradigm
Custom Computing Machines vs. Hardware/Software Codesign: From a globalized point of view
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
Reconfigurable RISC - A New Approach for Space-Efficient Superscalar Microprocessor Architecture
ARCS '02 Proceedings of the International Conference on Architecture of Computing Systems: Trends in Network and Pervasive Computing
ACAC '00 Proceedings of the 5th Australasian Computer Architecture Conference
Model-Based Exploration of the Design Space for Heterogeneous Systems on Chip
ASAP '02 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Reconfigurable Architectures for General-Purpose Computing
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IEEE Design & Test
Reliable event-triggered systems for mechatronic applications
Journal of Systems and Software - Special issue: Parallel and distributed real-time systems
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The universal configurable block/machine is a block-based approach for a configurable system-on-chip-(CSoC-) architecture. The programming model of the blocks is similar to microprocessor models, while the execution model supports configurable computing including reconfiguration. This is achieved by the microarchitecture of the blocks and an additional translation phase, resulting in three phases of overall program execution: fetching, translation and execution. These phases may act without strict coupling, simplifying the duplication of the executing part. The resulting hardware model is classified by four parameter: number of blocks, hyperblock sequencer, hyperblock scheduler and a set of block interconnections. The scheduler indicates that the model is capable of executing operating system work by scheduling hardware resources to threads or processes. This homogeneous CSoC may be used as compile-time defined inhomogeneous application-specific architecture. In this case the development process defines threads to run completely in one or more blocks solving partial problems and communicating to others. This enhances the flexibility and the optimization capabilities towards performance and/or real-time behavior.