Journal of Parallel and Distributed Computing
Hitting the memory wall: implications of the obvious
ACM SIGARCH Computer Architecture News
High-performance CMOS system design using wave pipelining
High-performance CMOS system design using wave pipelining
Computer Architecture: Pipelined and Parallel Processor Design
Computer Architecture: Pipelined and Parallel Processor Design
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Hardware/Software Co-Design
Optimum Instruction-level Parallelism (ILP) for Superscalar and VLIW Processors
Optimum Instruction-level Parallelism (ILP) for Superscalar and VLIW Processors
Latency-tolerant architectures
Latency-tolerant architectures
Vliw processors: efficiently exploiting instruction level parallelism
Vliw processors: efficiently exploiting instruction level parallelism
Computational Aspects of VLSI
Performance analysis and optimization of latency insensitive systems
Proceedings of the 37th Annual Design Automation Conference
Retargetable compiled simulation of embedded processors using a machine description language
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Implementing asynchronous circuits using a conventional EDA tool-flow
Proceedings of the 39th annual Design Automation Conference
Dual use of superscalar datapath for transient-fault detection and recovery
Proceedings of the 34th annual ACM/IEEE international symposium on Microarchitecture
Coping with Latency in SOC Design
IEEE Micro
Asynchronous First-in First-out Queues
PATMOS '00 Proceedings of the 10th International Workshop on Integrated Circuit Design, Power and Timing Modeling, Optimization and Simulation
Reconfigurable RISC - A New Approach for Space-Efficient Superscalar Microprocessor Architecture
ARCS '02 Proceedings of the International Conference on Architecture of Computing Systems: Trends in Network and Pervasive Computing
Fast processor core selection for WLAN modem using mappability estimation
Proceedings of the tenth international symposium on Hardware/software codesign
Optimizing pipelines for power and performance
Proceedings of the 35th annual ACM/IEEE international symposium on Microarchitecture
The Universal Configurable Block/Machine—An Approach for a Configurable SoC-Architecture
The Journal of Supercomputing
Optimum Power/Performance Pipeline Depth
Proceedings of the 36th annual IEEE/ACM International Symposium on Microarchitecture
Configware and morphware going mainstream
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Reconfigurable systems
Custom Wide Counterflow Pipelines for High-Performance Embedded Applications
IEEE Transactions on Computers
Uniprocessor Performance Enhancement through Adaptive Clock Frequency Control
IEEE Transactions on Computers
The optimum pipeline depth considering both power and performance
ACM Transactions on Architecture and Code Optimization (TACO)
Clustered Loop Buffer Organization for Low Energy VLIW Embedded Processors
IEEE Transactions on Computers
The impact of the nanoscale on computing systems
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Throttling-Based Resource Management in High Performance Multithreaded Architectures
IEEE Transactions on Computers
Transient fault prediction based on anomalies in processor events
Proceedings of the conference on Design, automation and test in Europe
Address Generation Optimization for Embedded High-Performance Processors: A Survey
Journal of Signal Processing Systems
UDSM trends comparison: from technology roadmap to UltraSparc Niagara2
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Deep-submicron technology allows billions of transistors on a single die, potentially running at GHz frequencies. Such robust technology leads to at least two separate processor optimization paradigms: server processors and client processors. High-end server processors will continue to evolve from current architectural trends. They will make gains in performance with significant increases in complexity. Performance is expected to improve marginally from increased ILP and, more significantly, from reduced cycle time but at the expense of power. On the other hand, commodity system-on-chip client processors will focus on functionality, power dissipation, cost, and other system-related issues. Both processor paradigms are expected to pay increased attention to reliability and overall computational integrity. Successful implementations depend on the processor architect's ability to foresee technology trends and understand the changing design trade-offs for their specific applications.