Communications of the ACM
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Handshake circuits: an asynchronous architecture for VLSI programming
Handshake circuits: an asynchronous architecture for VLSI programming
Four-phase micropipeline latch control circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Deep-Submicron Microprocessor Design Issues
IEEE Micro
Synthesis of 3D Asynchronous State Machines
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
An Asynchronous Low-Power 80C51 Microcontroller
ASYNC '98 Proceedings of the 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Asynchronous Design Using Commercial HDL Synthesis Tools
ASYNC '00 Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems
SYNTHESIS OF SELF-TIMED VLSI CIRCUITS FROM GRAPH-THEORETIC SPECIFICATIONS
SYNTHESIS OF SELF-TIMED VLSI CIRCUITS FROM GRAPH-THEORETIC SPECIFICATIONS
Practical verification and synthesis of low latency asynchronous systems
Practical verification and synthesis of low latency asynchronous systems
Automating the design of an asynchronous DLX microprocessor
Proceedings of the 40th annual Design Automation Conference
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
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This paper presents an approach by which asynchronous circuits can be realised with a conventional EDA tool flow and conventional standard cell libraries. Based on a gate-level asynchronous circuit implementation technique, direct-mapping, and by identifying the delay constraints and exploiting certain EDA tool features, this paper demonstrates that a conventional EDA tool flow can be used to describe, place, route and timing-verify asynchronous circuits.