Implementing asynchronous circuits using a conventional EDA tool-flow
Proceedings of the 39th annual Design Automation Conference
Design of Asynchronous Circuits Using Synchronous CAD Tools
IEEE Design & Test
Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Asynchronous on-Chip Communication: Explorations on the Intel PXA27x Processor Peripheral Bus
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
A GALS Infrastructure for a Massively Parallel Multiprocessor
IEEE Design & Test
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Outstanding research problems in NoC design: system, microarchitecture, and circuit perspectives
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fully-asynchronous low-power framework for GALS NoC integration
Proceedings of the Conference on Design, Automation and Test in Europe
Modeling Spiking Neural Networks on SpiNNaker
Computing in Science and Engineering
Spike-Based image processing: can we reproduce biological vision in hardware?
ECCV'12 Proceedings of the 12th international conference on Computer Vision - Volume Part I
Neural associative memories and sparse coding
Neural Networks
Proceedings of the Conference on Design, Automation and Test in Europe
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The design and implementation of globally asynchronous locally synchronous systems-on-chip is a challenging activity. The large size and complexity of the systems require the use of computer-aided design (CAD) tools but, unfortunately, most tools do not work adequately with asynchronous circuits. This article describes the successful design and implementation of SpiNNaker, a GALS multicore system-on-chip. The process was completed using commercial CAD tools from synthesis to layout. A hierarchical methodology was devised to deal with the asynchronous sections of the system, encapsulating and validating timing assumptions at each level. The crossbar topology combined with a pipelined asynchronous fabric implementation allows the on-chip network to meet the stringent requirements of the system. The implementation methodology constrains the design in a way that allows the tools to complete their tasks successfully. A first test chip, with reduced resources and complexity was taped-out using the proposed methodology. Test chips were received in December 2009 and were fully functional. The methodology had to be modified to cope with the increased complexity of the SpiNNaker SoC. SpiNNaker chips were delivered in May 2011 and were also fully operational, and the interconnect requirements were met.