Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A defect tolerant self-organizing nanoscale SIMD architecture
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Benchmarking mesh and hierarchical bus networks in system-on-chip context
Journal of Systems Architecture: the EUROMICRO Journal
A self-organizing defect tolerant SIMD architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
A Highly Scalable GALS Crossbar Using Token Ring Arbitration
IEEE Design & Test
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Developing mesochronous synchronizers to enable 3D NoCs
Proceedings of the conference on Design, automation and test in Europe
Practical asynchronous interconnect network design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low Static Powered Asynchronous Data Transfer for GALS System
IEICE - Transactions on Information and Systems
On NoC Bandwidth Sharing for the Optimization of Area Cost and Test Application Time
IEICE - Transactions on Information and Systems
GALS for Bursty Data Transfer based on Clock Coupling
Electronic Notes in Theoretical Computer Science (ENTCS)
VariPipe: low-overhead variable-clock synchronous pipelines
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Fault Modeling and Analysis for Resistive Bridging Defects in a Synchronizer
Journal of Electronic Testing: Theory and Applications
Asynchronous current mode serial communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Modeling and evaluation of ring-based interconnects for Network-on-Chip
Journal of Systems Architecture: the EUROMICRO Journal
Quasi delay-insensitive high speed two-phase protocol asynchronous wrapper for network on chips
Journal of Computer Science and Technology
Hermes-a - an asynchronous NoC router with distributed routing
PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Link pipelining strategies for an application-specific asynchronous NoC
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
SpiNNaker: Design and Implementation of a GALS Multicore System-on-Chip
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Benchmarking mesh and hierarchical bus networks in system-on-chip context
SAMOS'05 Proceedings of the 5th international conference on Embedded Computer Systems: architectures, Modeling, and Simulation
Testing of Synchronizers in Asynchronous FIFO
Journal of Electronic Testing: Theory and Applications
Proceedings of the Conference on Design, Automation and Test in Europe
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Asynchronous circuits can efficiently interconnect system-on-chip modules with different clock domains. Fulcrum's Nexus Interconnect features a 16-port, 36-bit asynchronous crossbar that connects through asynchronous channels to clock-domain converters for each synchronous module. In TSMC'S 130-nm process, Nexus achieves 1.35 GHz and transfers 780 Gbps.