Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Testing delay-insensitive circuits
Testing delay-insensitive circuits
Delay-Insensitive, Point-to-Point Interconnect Using M-of-N Codes
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Networks on chip
Reusing an on-chip network for the test of core-based systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Asynchronous Router for Multiple Service Levels Networks on Chip
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
A concurrent testing method for NoC switches
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Wrapper Design for the Reuse of Networks-on-Chip as Test Access Mechanism
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
A DFT Architecture for Asynchronous Networks-on-Chip
ETS '06 Proceedings of the Eleventh IEEE European Test Symposium
Principles of Asynchronous Circuit Design: A Systems Perspective
Principles of Asynchronous Circuit Design: A Systems Perspective
Test pattern generation and partial-scan methodology for an asynchronous SoC interconnect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bringing communication networks on a chip: test and verification implications
IEEE Communications Magazine
Indirect test architecture for SoC testing
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
| Hi-index | 0.00 |
Asynchronous design offers an attractive solution to overcome the problems faced by Networks-on-Chip (NoC) designers such as timing constraints. Nevertheless, post-fabrication testing is a big challenge to bring the asynchronous NoCs to the market due to a lack of testing methodology and support. This paper first presents the design and implementation of a Design-for-Test (DfT) architecture, which improves the testability of an asynchronous NoC architec-ture. Then, a simple method for generating test patterns for network routers is described. Test patterns are automatically generated by a custom program, given the network topology and the network size. Finally, we introduce a testing strategy for the whole asynchronous NoC. With the generated test patterns, the testing methodology presents high fault coverage (99.86%) for single stuck-at fault models.