An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework

Authors:
E. Beigne;F. Clermidy;P. Vivet;A. Clouard;M. Renaudin
Affiliations:
CEA-LETI;CEA-LETI;CEA-LETI;STMicroelectronics;TIMA Laboratory
Venue:
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Year:
2005

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Abstract

The demands of scalable, low latency and power efficient System-On-Chip interconnect cannot only be satisfied by point-to-point or shared-bus interconnects. In this paper, we propose a new AsynchronousNetwork-On-Chip (NOC) architecture which provides low latency transfers. This architecture is implemented as a GALS system, where chip units are built as synchronous islands, connected together using a Delay Insensitive asynchronous Network-on-Chip topology. The proposed NOC protocol and its asynchronous implementation are presented as well as the multi-level modeling approach using SystemC language andTransaction-Level-Modeling. Preliminary simulation results show that the Asynchronous NOC can offer 5 Gbytes/s throughput in a 0.13um CMOS technology.