An Asynchronous NOC Architecture Providing Low Latency Service and Its Multi-Level Design Framework
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
Die Stacking (3D) Microarchitecture
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture
A novel dimensionally-decomposed router for on-chip communication in 3D architectures
Proceedings of the 34th annual international symposium on Computer architecture
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
IEEE Transactions on Computers
Synthesis of networks on chips for 3D systems on chips
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application
DSD '09 Proceedings of the 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools
A fully-asynchronous low-power framework for GALS NoC integration
Proceedings of the Conference on Design, Automation and Test in Europe
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Three-dimensional networks-on-chip (3D NoC) are rising as a good approach to well managed complex interconnections in 3D multi-processor system-on-chip (MPSoC). This paper introduces a new router in order to enhance throughput and latency compared to classic 3D mesh NoC. The proposed router is hierarchical as it is composed of two completely decoupled modules: one for inter-layer communication and one for intra-layer communication. It is fully implemented in asynchronous logic to allow low latency transfer. Synthesis and extrapolation results show that the hierarchical router is competitive with the classic 3D mesh in terms of area and power. Throughput and latency evaluation is performed using a SystemC-TLM NoC simulator. Simulations' results show that the proposed hierarchical router can outperform the 3D mesh by more than 25% in terms of throughput and latency in the case of transpose traffic. Copyright © 2012 John Wiley & Sons, Ltd.