Scalability of network-on-chip communication architecture for 3-D meshes
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Hybrid wireless Network on Chip: a new paradigm in multi-core design
Proceedings of the 2nd International Workshop on Network on Chip Architectures
From 2D to 3D NoCs: a case study on worst-case communication performance
Proceedings of the 2009 International Conference on Computer-Aided Design
IEEE Transactions on Circuits and Systems II: Express Briefs
3D network-on-chip architectures using homogeneous meshes and heterogeneous floorplans
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
3D floorplanning of low-power and area-efficient Network-on-Chip architecture
Microprocessors & Microsystems
Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Cluster-based topologies for 3D stacked architectures
Proceedings of the 8th ACM International Conference on Computing Frontiers
Power and area optimization of 3D networks-on-chip using smart and efficient vertical channels
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
Power-aware run-time incremental mapping for 3-D networks-on-chip
NPC'11 Proceedings of the 8th IFIP international conference on Network and parallel computing
3D NOC for many-core processors
Microelectronics Journal
A novel graceful degradable routing algorithm for 3D on-chip networks
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems
Journal of Electronic Testing: Theory and Applications
CMOS compatible many-core noc architectures with multi-channel millimeter-wave wireless links
Proceedings of the great lakes symposium on VLSI
A novel 3D NoC architecture based on De Bruijn graph
Computers and Electrical Engineering
Refinement-Based modeling of 3d nocs
FSEN'11 Proceedings of the 4th IPM international conference on Fundamentals of Software Engineering
Software—Practice & Experience
An efficient routing technique for mesh-of-tree-based NoC and its performance comparison
International Journal of High Performance Systems Architecture
Design and evaluation of Mesh-of-Tree based Network-on-Chip using virtual channel router
Microprocessors & Microsystems
Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels
Journal of Computer and System Sciences
Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture
Journal of Computer and System Sciences
Wireless interconnect for board and chip level
Proceedings of the Conference on Design, Automation and Test in Europe
Thermal-constrained task allocation for interconnect energy reduction in 3-D homogeneous MPSoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CusNoC: fast full-chip custom NoC generation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
New heuristic algorithms for low-energy mapping and routing in 3D NoC
International Journal of Computer Applications in Technology
Complex network-enabled robust wireless network-on-chip architectures
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Optimal placement of vertical connections in 3D Network-on-Chip
Journal of Systems Architecture: the EUROMICRO Journal
The Journal of Supercomputing
Transport-layer-assisted routing for runtime thermal management of 3D NoC systems
ACM Transactions on Embedded Computing Systems (TECS)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Towards optimal adaptive routing in 3D NoC with limited vertical bandwidth
Proceedings of the Sixth International Workshop on Network on Chip Architectures
Power consumption of 3D networks-on-chips: Modeling and optimization
Microprocessors & Microsystems
An Analysis of Reducing Communication Delay in Network-on-Chip Interconnect Architecture
Wireless Personal Communications: An International Journal
Virtualized and fault-tolerant inter-layer-links for 3D-ICs
Microprocessors & Microsystems
TM: a new and simple topology for interconnection networks
The Journal of Supercomputing
High-speed dynamic TDMA arbiter for inter-layer communications in 3-D network-on-chip
Journal of High Speed Networks
| Hi-index | 14.98 |
The Network-on-Chip (NoC) paradigm has emerged as a revolutionary methodology for integrating a very high number of intellectual property (IP) blocks in a single die. The achievable performance benefit arising out of adopting NoCs is constrained by the performance limitation imposed by the metal wire, which is the physical realization of communication channels. With technology scaling, only depending on the material innovation will extend the lifetime of conventional interconnect systems a few technology generations. According to International Technology Roadmap for Semiconductors (ITRS) for the longer term, new interconnect paradigms are in need. The conventional two dimensional (2D) integrated circuit (IC) has limited floor-planning choices, and consequently it limits the performance enhancements arising out of NoC architectures. Three dimensional (3D) ICs are capable of achieving better performance, functionality, and packaging density compared to more traditional planar ICs. On the other hand, NoC is an enabling solution for integrating large numbers of embedded cores in a single die. 3D NoC architectures combine the benefits of these two new domains to offer an unprecedented performance gain. In this paper we evaluate the performance of 3D NoC architectures and demonstrate their superior functionality in terms of throughput, latency, energy dissipation and wiring area overhead compared to traditional 2D implementations.