Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
High Level Synthesis of Degradable ASICs Using Virtual Binding
VTS '07 Proceedings of the 25th IEEE VLSI Test Symmposium
Networks-on-Chip in a Three-Dimensional Environment: A Performance Evaluation
IEEE Transactions on Computers
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Fault tolerant network on chip switching with graceful performance degradation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
A highly resilient routing algorithm for fault-tolerant NoCs
Proceedings of the Conference on Design, Automation and Test in Europe
Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC
BWCCA '10 Proceedings of the 2010 International Conference on Broadband, Wireless Computing, Communication and Applications
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The decreasing manufacturing yield of integrated circuits, as a result of rising complexity and decreased feature size, and the emergence of 3D-NoC based design architectures, has necessitated the search for network reconfiguration techniques in order to make faulty networks reusable. In this paper, we first introduce an efficient and scalable hardware based on using a fixed size programmable routing table (PRT) for each network switch. Then a heuristic search algorithm is provided to find a valid configuration for these PRTs and to compensate the effects of faulty links in three dimensional networks on chip. Our experimental results show that the algorithm considerably reduces the required search effort as compared to the exhaustive search method.