Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
ATS '02 Proceedings of the 11th Asian Test Symposium
ICPP '02 Proceedings of the 2002 International Conference on Parallel Processing
A fault model notation and error-control scheme for switch-to-switch buses in a network-on-chip
Proceedings of the 1st IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Cyclic Redundancy Code (CRC) Polynomial Selection For Embedded Networks
DSN '04 Proceedings of the 2004 International Conference on Dependable Systems and Networks
On-Chip Stochastic Communication
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Networks on which hot-potato routing does not livelock
Distributed Computing
Part I: A Theory for Deadlock-Free Dynamic Network Reconfiguration
IEEE Transactions on Parallel and Distributed Systems
Part II: A Methodology for Developing Deadlock-Free Dynamic Network Reconfiguration Processes
IEEE Transactions on Parallel and Distributed Systems
Packet Routing in Dynamically Changing Networks on Chip
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Analysis of Error Recovery Schemes for Networks on Chips
IEEE Design & Test
An event-based monitoring service for networks on chip
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Evaluation of on-chip networks using deflection routing
GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip
Proceedings of the 43rd annual Design Automation Conference
A High Level Power Model for the Nostrum NoC
DSD '06 Proceedings of the 9th EUROMICRO Conference on Digital System Design
On-line Fault Detection and Location for NoC Interconnects
IOLTS '06 Proceedings of the 12th IEEE International Symposium on On-Line Testing
Test Configurations for Diagnosing Faulty Links in NoC Switches
ETS '07 Proceedings of the 12th IEEE European Test Symposium
Online NoC Switch Fault Detection and Diagnosis Using a High Level Fault Model
DFT '07 Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip
Proceedings of the 45th annual Design Automation Conference
Accuracy-adaptive simulation of transaction level models
Proceedings of the conference on Design, automation and test in Europe
BARP-a dynamic routing protocol for balanced distribution of traffic in NoCs
Proceedings of the conference on Design, automation and test in Europe
The Future of Computer Technology and its Implications for the Computer Industry
The Computer Journal
Efficient Application Specific Routing Algorithms for NoC Systems utilizing Partially Faulty Links
DSD '08 Proceedings of the 2008 11th EUROMICRO Conference on Digital System Design Architectures, Methods and Tools
A new mechanism to deal with process variability in NoC links
IPDPS '09 Proceedings of the 2009 IEEE International Symposium on Parallel&Distributed Processing
Fault-tolerant architecture and deflection routing for degradable NoC switches
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
International Journal of High Performance Systems Architecture
Error control schemes for on-chip communication links: the energy-reliability tradeoff
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Interconnect Test Patterns for Crosstalk and Static Faults
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fault-tolerant NoC scheme using bidirectional channel
Proceedings of the 48th Design Automation Conference
A novel graceful degradable routing algorithm for 3D on-chip networks
Proceedings of the 2012 Interconnection Network Architecture: On-Chip, Multi-Chip Workshop
Structural Test and Diagnosis for Graceful Degradation of NoC Switches
Journal of Electronic Testing: Theory and Applications
NoCAlert: An On-Line and Real-Time Fault Detection Mechanism for Network-on-Chip Architectures
MICRO-45 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture
A unified link-layer fault-tolerant architecture for network-based many-core embedded systems
Journal of Systems Architecture: the EUROMICRO Journal
Journal of Systems Architecture: the EUROMICRO Journal
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
A first effort for a distributed segment-based approach on self-assembled nano networks
Proceedings of the Sixth International Workshop on Network on Chip Architectures
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The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity even if network components are out of service due to faults, which will appear at an increasing rate with future chip technology nodes. This paper is based on a new, fine-grained functional fault model and a corresponding distributed fault diagnosis method that facilitate determining the fault status of individual NoC switches and their adjacent communication links. Whereas previous work on network fault-tolerance assume switches to be either available or fully out of service, we present a novel adaptive routing algorithm that employs the remaining functionality of partly defective switches. Using diagnostic information, transient faults are handled with a retransmission scheme that avoids the latency penalty of end-to-end repeat requests. Thereby, graceful degradation of NoC communication performance can be achieved even under high failure rates.