Highly compact interconnect test patterns for crosstalk and static faults
IEEE Transactions on Circuits and Systems II: Express Briefs
Highly compact interconnect test patterns for crosstalk and static faults
IEEE Transactions on Circuits and Systems II: Express Briefs
Fault tolerant network on chip switching with graceful performance degradation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
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This paper introduces effective test patterns for system-on-chip and board interconnects. Initially, "6n" patterns are introduced to completely detect and diagnose both static and crosstalk faults, where "n" is the total number of interconnect nets. Then, more economic "4n+1" patterns are described to test the crosstalk faults for the interconnect nets separated within a certain distance