A Theory of Fault-Tolerant Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
Layered Shortest Path (LASH) Routing in Irregular System Area Networks
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
A Flexible Routing Scheme for Networks of Workstations
ISHPC '00 Proceedings of the Third International Symposium on High Performance Computing
Fibre Channel Fabrics: Evaluation and Design
HICSS '96 Proceedings of the 29th Hawaii International Conference on System Sciences Volume 1: Software Technology and Architecture
Effective Methodology for Deadlock-Free Minimal Routing in InfiniBand Networks
ICPP '02 Proceedings of the 2002 International Conference on Parallel Processing
LASH-TOR: A Generic Transition-Oriented Routing Algorithm
ICPADS '04 Proceedings of the Parallel and Distributed Systems, Tenth International Conference
An Efficient Fault-Tolerant Routing Methodology for Meshes and Tori
IEEE Computer Architecture Letters
NANA: A nano-scale active network architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Logic-Based Distributed Routing for NoCs
IEEE Computer Architecture Letters
A Lightweight Fault-Tolerant Mechanism for Network-on-Chip
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Architectural implications of nanoscale integrated sensing and computing
Proceedings of the 14th international conference on Architectural support for programming languages and operating systems
Routing in self-organizing nano-scale irregular networks
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Fault tolerant network on chip switching with graceful performance degradation
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems - Special issue on the 2009 ACM/IEEE international symposium on networks-on-chip
Segment-based routing: an efficient fault-tolerant routing algorithm for meshes and Tori
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
A resilient on-chip router design through data path salvaging
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Autonet: a high-speed, self-configuring local area network using point-to-point links
IEEE Journal on Selected Areas in Communications
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In this paper we present DiSR, a first effort for a distributed segment-based approach to routing and defect mapping in a nano-scale, topology agnostic scenario based on DNA self-assembly. The main aim is exploiting the already-proven qualities of segment-based routing without neither requiring a topology graph as input, nor needing a centralized algorithm to configure network paths. After introducing the conceptual elements and the execution model of DiSR, we show how the opensource Nanoxim platform has been used to evaluate the proposed approach in the process of discovering irregular network topology while establishing network segments. Results show how DiSR still preserves some important properties (coverage, defect tolerance, scalability) while avoiding centralized tree-based broadcasting and resource hungry solutions such as virtual channels and hardware redundancy. Finally, we analyzed a first, not yet optimised gate-level hardware implementation of the required control logic and storage for DiSR, demonstrating a relatively acceptable impact ranging from 10 to about 20% of the budget of transistors available for each node.