L-Turn Routing: An Adaptive Routing in Irregular Networks
ICPP '02 Proceedings of the 2001 International Conference on Parallel Processing
Layered Shortest Path (LASH) Routing in Irregular System Area Networks
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
ISHPC '00 Proceedings of the Third International Symposium on High Performance Computing
A Flexible Routing Scheme for Networks of Workstations
ISHPC '00 Proceedings of the Third International Symposium on High Performance Computing
Fibre Channel Fabrics: Evaluation and Design
HICSS '96 Proceedings of the 29th Hawaii International Conference on System Sciences Volume 1: Software Technology and Architecture
Effective Methodology for Deadlock-Free Minimal Routing in InfiniBand Networks
ICPP '02 Proceedings of the 2002 International Conference on Parallel Processing
The Quadrics Network (QsNet): High-Performance Clustering Technology
HOTI '01 Proceedings of the The Ninth Symposium on High Performance Interconnects
LASH-TOR: A Generic Transition-Oriented Routing Algorithm
ICPADS '04 Proceedings of the Parallel and Distributed Systems, Tenth International Conference
Improving InfiniBand Routing through Multiple Virtual Networks
ISHPC '02 Proceedings of the 4th International Symposium on High Performance Computing
Simple deadlock-free dynamic network reconfiguration
HiPC'04 Proceedings of the 11th international conference on High Performance Computing
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Deadlock free routing algorithms for irregular mesh topology NoC systems with rectangular regions
Journal of Systems Architecture: the EUROMICRO Journal
Improving communication-phase completion times in HPC clusters through congestion mitigation
SYSTOR '09 Proceedings of SYSTOR 2009: The Israeli Experimental Systems Conference
HiRA: A methodology for deadlock free routing in hierarchical networks on chip
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
A Multipath Fault-Tolerant Routing Method for High-Speed Interconnection Networks
Euro-Par '09 Proceedings of the 15th International Euro-Par Conference on Parallel Processing
Region-based routing: a mechanism to support efficient routing algorithms in NoCs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Computer Networks: The International Journal of Computer and Telecommunications Networking
Compiler directed network-on-chip reliability enhancement for chip multiprocessors
Proceedings of the ACM SIGPLAN/SIGBED 2010 conference on Languages, compilers, and tools for embedded systems
On disconnection node failure and stochastic static resilience of P2P communication networks
ICCSA'07 Proceedings of the 2007 international conference on Computational science and its applications - Volume Part III
Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A deadlock-free routing algorithm for dynamically reconfigurable Networks-on-Chip
Microprocessors & Microsystems
An abacus turn model for time/space-efficient reconfigurable routing
Proceedings of the 38th annual international symposium on Computer architecture
DRAIN: distributed recovery architecture for inaccessible nodes in multi-core chips
Proceedings of the 48th Design Automation Conference
Tree-turn routing: an efficient deadlock-free routing algorithm for irregular networks
The Journal of Supercomputing
A hardware supported multicast scheme based on XY routing for 2-D mesh InfiniBand networks
The Journal of Supercomputing
Application-aware deadlock-free oblivious routing based on extended turn-model
Proceedings of the International Conference on Computer-Aided Design
A scalable and fault-tolerant network routing scheme for many-core and multi-chip systems
Journal of Parallel and Distributed Computing
Cost-effective contention avoidance in a CMP with shared memory controllers
Euro-Par'12 Proceedings of the 18th international conference on Parallel Processing
Allocating irregular partitions in mesh-based on-chip networks
Euro-Par'12 Proceedings of the 18th international conference on Parallel processing workshops
Addressing link degradation in noc-based ULSI designs
Euro-Par'12 Proceedings of the 18th international conference on Parallel processing workshops
A fast algorithm for runtime reconfiguration to maximize the lifetime of nanoscale NoCs
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip
An efficient, low-cost routing framework for convex mesh partitions to support virtualization
ACM Transactions on Embedded Computing Systems (TECS) - Special Section on Wireless Health Systems, On-Chip and Off-Chip Network Architectures
RISO: relaxed network-on-chip isolation for cloud processors
Proceedings of the 50th Annual Design Automation Conference
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
A first effort for a distributed segment-based approach on self-assembled nano networks
Proceedings of the Sixth International Workshop on Network on Chip Architectures
uDIREC: unified diagnosis and reconfiguration for frugal bypass of NoC faults
Proceedings of the 46th Annual IEEE/ACM International Symposium on Microarchitecture
Non-minimal, turn-model based NoC routing
Microprocessors & Microsystems
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Computers get faster every year, but the demand for computing resources seems to grow at an even faster rate. Depending on the problem domain, this demand for more power can be satisfied by either, massively parallel computers, or clusters of computers. Common for both approaches is the dependence on high performance interconnect networks such as Myrinet, Infiniband, or 10 Gigabit Ethernet. While high throughput and low latency are key features of interconnection networks, the issue of faul-ttolerance is now becoming increasingly important. As the number of network components grows so does the probability for failure, thus it becomes important to also consider the fault-tolerance mechanism of interconnection networks. The main challenge then lies in combining performance and fault-tolerance, while still keeping cost and complexity low. This paper proposes a new deterministic routing methodology for tori and meshes, which achieves high performance without the use of virtual channels. Furthermore, it is topology agnostic in nature, meaning it can handle any topology derived from any combination of faults when combined with static reconfiguration. The algorithm, referred to as Segment-based Routing (SR), works by partitioning a topology into subnets, and subnets into segments. This allows us to place bidirectional turn restrictions locally within a segment. As segments are independent, we gain the freedom to place turn restrictions within a segment independently from other segments. This results in a larger degree of freedom when placing turn restrictions compared to other routing strategies. In this paper a way to compute segment-based routing tables is presented and applied to meshes and tori. Evaluation results show that SR increases performance by a factor of 1.8 over FX and up*/down* routing.