A fast algorithm for runtime reconfiguration to maximize the lifetime of nanoscale NoCs

Authors:
Francisco Triviño;Davide Bertozzi;José Flich
Affiliations:
Universidad de Castilla-La Mancha, Albacete, Spain;University of Ferrara, Ferrara, Italy;Universitat Politècnica de València, Valencia, Spain
Venue:
Proceedings of the 2013 Interconnection Network Architecture: On-Chip, Multi-Chip
Year:
2013

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Abstract

In this paper, we propose a fast algorithm to reprogram the routing function of an on-chip network (NoC) at runtime. This reconfiguration algorithm comes with the following key novelties. First, it deals with the lack of routing tables, which are poorly scalable and lengthy to reconfigure. Second, it can deal with any number of faults that might be progressively detected over time (i.e., full coverage of fault patterns). Third, it preserves ultra-fast reconfiguration times even for the most challenging scenarios.