Optimal fully adaptive wormhole routing for meshes
Proceedings of the 1993 ACM/IEEE conference on Supercomputing
The turn model for adaptive routing
Journal of the ACM (JACM)
An efficient, fully adaptive deadlock recovery scheme: DISHA
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
A Fault-Tolerant and Deadlock-Free Routing Protocol in 2D Meshes Based on Odd-Even Turn Model
IEEE Transactions on Computers
Packetization and routing analysis of on-chip multiprocessor networks
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
DyAD: smart routing for networks-on-chip
Proceedings of the 41st annual Design Automation Conference
Load Distribution with the Proximity Congestion Awareness in a Network on Chip
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Performance Evaluation and Design Trade-Offs for Network-on-Chip Interconnect Architectures
IEEE Transactions on Computers
IEEE Transactions on Parallel and Distributed Systems
Deadlock-free routing and component placement for irregular mesh-based networks-on-chip
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Designing efficient irregular networks for heterogeneous systems-on-chip
Journal of Systems Architecture: the EUROMICRO Journal
Implementation and Analysis of a New Selection Strategy for Adaptive Routing in Networks-on-Chip
IEEE Transactions on Computers
Traffic-Balanced Routing Algorithm for Irregular Mesh-Based On-Chip Networks
IEEE Transactions on Computers
A case for bufferless routing in on-chip networks
Proceedings of the 36th annual international symposium on Computer architecture
Evaluating Bufferless Flow Control for On-chip Networks
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Increasing the adaptivity of routing algorithms for k-ary n-cubes
EUROMICRO-PDP'02 Proceedings of the 10th Euromicro conference on Parallel, distributed and network-based processing
Segment-based routing: an efficient fault-tolerant routing algorithm for meshes and Tori
IPDPS'06 Proceedings of the 20th international conference on Parallel and distributed processing
System-Level Buffer Allocation for Application-Specific Networks-on-Chip Router Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Bidirectional NoC (BiNoC) Architecture With Dynamic Self-Reconfigurable Channel
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Autonet: a high-speed, self-configuring local area network using point-to-point links
IEEE Journal on Selected Areas in Communications
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In this study, it is shown that any deadlock-free, turn-model based minimal routing algorithm can be extended to a non-minimal routing algorithm. Specifically, three novel non-minimal NoC routing algorithms are proposed based on the Odd-Even, West-First, and Negative-First turn models, respectively. These algorithms are not only deadlock free and livelock free, but can also leverage non-minimal routing paths to avoid traffic congestion and improve fault tolerance. Moreover, these algorithms are backward compatible with existing minimal routing schemes. As a result, they represent an ideal routing solution to NoC-based interconnections designed for both existing and emerging embedded multicore systems.