Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
Scheduling algorithms for input-queued cell switches
Scheduling algorithms for input-queued cell switches
On deadlocks in interconnection networks
Proceedings of the 24th annual international symposium on Computer architecture
Proceedings of the 6th international workshop on Hardware/software codesign
Adaptive-Trail Routing and Performance Evaluation in Irregular Networks Using Cut-Through Switches
IEEE Transactions on Parallel and Distributed Systems
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
The Message Flow Model for Routing in Wormhole-Routed Networks
IEEE Transactions on Parallel and Distributed Systems
Filtering Random Graphs to Synthesize Interconnection Networks with Multiple Objectives
IEEE Transactions on Parallel and Distributed Systems
ServerNet Deadlock Avoidance and Fractahedral Topologies
IPPS '96 Proceedings of the 10th International Parallel Processing Symposium
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
HPCA '03 Proceedings of the 9th International Symposium on High-Performance Computer Architecture
Characterization of Deadlocks in Irregular Networks
ICPP '99 Proceedings of the 1999 International Conference on Parallel Processing
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture
DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Bandwidth-Constrained Mapping of Cores onto NoC Architectures
Proceedings of the conference on Design, automation and test in Europe - Volume 2
SUNMAP: a tool for automatic topology selection and generation for NoCs
Proceedings of the 41st annual Design Automation Conference
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
Application-specific network-on-chip architecture customization via long-range link insertion
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Performance of Processor-Memory Interconnections for Multiprocessors
IEEE Transactions on Computers
Performance Analysis of a Packet Switch Based on Single-Buffered Banyan Network
IEEE Journal on Selected Areas in Communications
Flexible interconnection network for dynamically and partially reconfigurable architectures
International Journal of Reconfigurable Computing - Special issue on selected papers from spl 2009 programmable logic and applications
Adaptive and deadlock-free tree-based multicast routing for networks-on-chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
3D network-on-chip architectures using homogeneous meshes and heterogeneous floorplans
International Journal of Reconfigurable Computing - Special issue on selected papers from ReconFig 2009 International conference on reconfigurable computing and FPGAs (ReconFig 2009)
Journal of Systems Architecture: the EUROMICRO Journal
Non-minimal, turn-model based NoC routing
Microprocessors & Microsystems
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Networks-on-chip will serve as the central integration platform in future complex systems-on-chip (SoC) designs, composed of a large number of heterogeneous processing resources. Most researchers advocate the use of traditional regular networks like meshes, tori or trees as architectural templates which gained a high popularity in general-purpose parallel computing. However, most SoC platforms are special-purpose tailored to the domain-specific requirements of their application. They are usually built from a large diversity of heterogeneous components which communicate in a very specific, mostly irregular way. In this work, we propose a methodology for the design of customized irregular networks-on-chip, called INoC. We take advantage of a priori knowledge of the communication characteristic of the application to generate an optimized network topology and routing algorithm. We show that customized irregular networks are clearly superior to traditional regular architectures in terms of performance at comparable implementation costs for irregular workloads. Even more, they inherently offer a high degree of scalability and expansibility which allows to adapt the network to an arbitrary number of nodes with a given communication demand. This can normally not be accomplished by traditional approaches.