Deadlock-Free Message Routing in Multiprocessor Interconnection Networks
IEEE Transactions on Computers
The turn model for adaptive routing
ISCA '92 Proceedings of the 19th annual international symposium on Computer architecture
A New Theory of Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
A General Theory for Deadlock Avoidance in Wormhole-Routed Networks
IEEE Transactions on Parallel and Distributed Systems
A generic architecture for on-chip packet-switched interconnections
DATE '00 Proceedings of the conference on Design, automation and test in Europe
The Odd-Even Turn Model for Adaptive Routing
IEEE Transactions on Parallel and Distributed Systems
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Route packets, not wires: on-chip inteconnection networks
Proceedings of the 38th annual Design Automation Conference
A Cost-Effective Approach to Deadlock Handling in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
Interconnection Networks: An Engineering Approach
Interconnection Networks: An Engineering Approach
A Necessary and Sufficient Condition for Deadlock-Free Adaptive Routing in Wormhole Networks
IEEE Transactions on Parallel and Distributed Systems
Performance Analysis of Minimal Adaptive Wormhole Routing with Time-Dependent Deadlock Recovery
IPPS '97 Proceedings of the 11th International Symposium on Parallel Processing
Interconnect IP Node for Future System-on-Chip Designs
DELTA '02 Proceedings of the The First IEEE International Workshop on Electronic Design, Test and Applications (DELTA '02)
Networks on Silicon: Blessing or Nightmare?
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
SoCBUS: Switched Network on Chip for Hard Real Time Embedded Systems
IPDPS '03 Proceedings of the 17th International Symposium on Parallel and Distributed Processing
High-level Architectural Simulation of the Torus Routing Chip
IVC '97 Proceedings of the 1997 IEEE International Verilog HDL Conference (IVC '97)
A Network on Chip Architecture and Design Methodology
ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
IEEE Transactions on Parallel and Distributed Systems
A Fault-Tolerant and Deadlock-Free Routing Protocol in 2D Meshes Based on Odd-Even Turn Model
IEEE Transactions on Computers
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms
Computers and Electrical Engineering
A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
Routing table minimization for irregular mesh NoCs
Proceedings of the conference on Design, automation and test in Europe
Multicast parallel pipeline router architecture for network-on-chip
Proceedings of the conference on Design, automation and test in Europe
A Communication-Aware Topological Mapping Technique for NoCs
Euro-Par '08 Proceedings of the 14th international Euro-Par conference on Parallel Processing
Link-load balance aware mapping and routing for NoC
WSEAS Transactions on Circuits and Systems
Routing in self-organizing nano-scale irregular networks
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
A Low-Cost Deadlock-Free Design of Minimal-Table Rerouted XY-Routing for Irregular Wireless NoCs
NOCS '10 Proceedings of the 2010 Fourth ACM/IEEE International Symposium on Networks-on-Chip
Efficient routing implementation in complex systems-on-chip designs
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
A3MAP: Architecture-aware analytic mapping for networks-on-chip
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on verification challenges in the concurrent world
Methods for fault tolerance in networks-on-chip
ACM Computing Surveys (CSUR)
Power and Latency Optimized Deadlock-Free Routing Algorithm on Irregular 2D Mesh NoC using LBDRe
International Journal of Embedded and Real-Time Communication Systems
Non-minimal, turn-model based NoC routing
Microprocessors & Microsystems
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Routing is one of the most crucial key factors which decides over the success of NoC architecture based systems or their failure. This paper uses well known principles from parallel computer architecture to develop a deadlock free highly adaptive routing algorithm for a 2D-mesh based network-on-chip (NoC) architecture including oversized IP cores. The paper consists of a short introduction into related routing theories and then gives a detailed description of the developed routing scheme. The last part is dedicated to a new floorplanning method, which allows to generate high density layouts suitable for the presented routing algorithm.