Link-load balance aware mapping and routing for NoC

Authors:
Zhou Wenbiao;Yan Zhang;Zhigang Mao
Affiliations:
Harbin Institute of Technology Shenzhen Graduate School, SoC Research Center, Shenzhen, Guangzhou, China and Microelectronics Center, Harbin, Heilongjiang;Harbin Institute of Technology Shenzhen Graduate School, SoC Research Center, Shenzhen, Guangzhou, China;Harbin Institute of Technology, Microelectronics Center, Harbin, Heilongjiang, China
Venue:
WSEAS Transactions on Circuits and Systems
Year:
2007

Citing 17
Cited 5

TGFF: task graphs for free

Proceedings of the 6th international workshop on Hardware/software codesign
Route packets, not wires: on-chip inteconnection networks

Proceedings of the 38th annual Design Automation Conference
Networks on Chips: A New SoC Paradigm

Computer
Networks on Silicon: Blessing or Nightmare?

DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
A Network on Chip Architecture and Design Methodology

ISVLSI '02 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Networks on chip

Networks on chip
A Two-step Genetic Algorithm for Mapping Task Graphs to a Network on Chip Architecture

DSD '03 Proceedings of the Euromicro Symposium on Digital Systems Design
Bandwidth-Constrained Mapping of Cores onto NoC Architectures

Proceedings of the conference on Design, automation and test in Europe - Volume 2
Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Many-to-Many Core-Switch Mapping in 2-D Mesh NoC Architectures

ICCD '04 Proceedings of the IEEE International Conference on Computer Design
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip

IEEE Transactions on Parallel and Distributed Systems
ISIS: A Genetic Algorithm Based Technique for Custom On-Chip Interconnection Network Synthesis

VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
A technique for low energy mapping and routing in network-on-chip architectures

ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Key research problems in NoC design: a holistic perspective

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Deadlock-free routing and component placement for irregular mesh-based networks-on-chip

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Low-power network-on-chip for high-performance SoC design

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Linear-programming-based techniques for synthesis of network-on-chip architectures

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Benchmarking in digital circuit design automation

WSEAS Transactions on Circuits and Systems
The era of many-modules SoC: revisiting the NoC mapping problem

Proceedings of the 2nd International Workshop on Network on Chip Architectures
An insertion loss balance aware routing scheme in photonic network on chip

ICICS'09 Proceedings of the 7th international conference on Information, communications and signal processing
HACS: A novel cost aware paradigm promising fault tolerance on mesh-based network on chip architecture

Computers and Electrical Engineering
A survey on application mapping strategies for Network-on-Chip design

Journal of Systems Architecture: the EUROMICRO Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, a cross-coupled type AC-DC converter for RFID tags is proposed. The converter consists of 2 charge-pump type AC-DC converters with opposite polarities. In conventional converters, the threshold voltage of a diode switch causes the decrease ...