Guaranteeing the quality of services in networks on chip
Networks on chip
A Flexible and Energy-Efficient Coarse-Grained Reconfigurable Architecture for Mobile Systems
The Journal of Supercomputing
Proceedings of the conference on Design, automation and test in Europe - Volume 2
QNoC: QoS architecture and design process for network on chip
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Networks on chip
NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip
IEEE Transactions on Parallel and Distributed Systems
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Cost considerations in network on chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Architecture and performance comparison of a statistic-based lottery arbiter for shared bus on chip
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Deadlock-free routing and component placement for irregular mesh-based networks-on-chip
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
A priority assignment strategy of processing elements over an on-chip bus
Proceedings of the 2007 ACM symposium on Applied computing
Advanced hardware/software co-design on reconfigurable network-on-chip based hyper-platforms
Computers and Electrical Engineering
Proceedings of the conference on Design, automation and test in Europe
QoS-supported on-chip communication for multi-processors
International Journal of Parallel Programming - Special Issue on Multiprocessor-based embedded systems
Application-driven floorplan-aware voltage island design
Proceedings of the 45th annual Design Automation Conference
A Link-Load Balanced Low Energy Mapping and Routing for NoC
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
An Efficient Implementation Method of Arbiter for the ML-AHB Busmatrix
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
Link-load balance aware mapping and routing for NoC
WSEAS Transactions on Circuits and Systems
Application-driven voltage-island partitioning for low-power system-on-chip design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Modelling and evaluation of a network on chip architecture using SDL
SDL'03 Proceedings of the 11th international conference on System design
Reconfigurable Networks on Chip: DRNoC architecture
Journal of Systems Architecture: the EUROMICRO Journal
Priority-based packet communication on a bus-shaped structure for FPGA-systems
Proceedings of the Conference on Design, Automation and Test in Europe
Virtualizing network-on-chip resources in chip-multiprocessors
Microprocessors & Microsystems
A workload-adaptive and reconfigurable bus architecture for multicore processors
International Journal of Reconfigurable Computing
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Continuing VLSI technology scaling raises several deep submicron (DSM) problems like relatively slow interconnect, power dissipation and distribution. and signal integrity. Those problems are encountered particularly on long wires for global interconnect. As clockfrequencies increase, scaled wires become relatively slower; and on-chip communication will be the limiting performance factor of future chips. We explain why efficiently sharing of the wires for long distance communication is the solution to this problem. We introduce networks on silicon (NoS), that route packets over shared ( semi)- global wires. NoS performance is expected to be high, but comes at a cost. Balancing the performance and cost of a NoS is a major challenge, and we believe busses still have a role play.