AMBA: Enabling Reusable On-Chip Designs
IEEE Micro
Networks on Silicon: Blessing or Nightmare?
DSD '02 Proceedings of the Euromicro Symposium on Digital Systems Design
aSOC: A Scalable, Single-Chip Communications Architecture
PACT '00 Proceedings of the 2000 International Conference on Parallel Architectures and Compilation Techniques
Implementation of a self-motivated arbitration scheme for the multilayer ARB busmatrix
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The multi-layer AHB busmatrix (ML-AHB busmatrix) proposed by ARM is a highly efficient on chip bus that allows parallel access paths between multiple masters and slaves in a system. In this paper, we present one way to improve the arbiter implementation of the ML-AHB busmatrix. We employ the masking mechanism which does not impose any restrictions on arbitration scheme. Therefore, the proposed scheme is applied to the implementation of busmatrixes to support the transaction based arbitrations as well as the transfer based arbitrations. In addition, we could not only enhance the throughput of bus system but also reduce the total area, clock period and power consumption. Experimental results show that the throughput of our busmatrix based on the transfer based fixed priority (round robin) arbitration scheme is increased by 41% (18%) compared with that of the equivalent busmatrix of ARM. Moreover, we could reduce the total area, clock period and power consumption by 22%, 28% and 19% (12%, 15% and 13%) respectively, compared with the busmatrix employing the transfer based fixed priority (round robin) arbitration scheme of ARM.