AMBA: Enabling Reusable On-Chip Designs
IEEE Micro
Performance Analysis of Systems with Multi-Channel Communication Architectures
VLSID '00 Proceedings of the 13th International Conference on VLSI Design
Asynchronous Layered Interface of Multimedia SoCs for Multiple Outstanding Transactions
Journal of VLSI Signal Processing Systems
Proceedings of the 2007 ACM symposium on Applied computing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Slack-based Bus Arbitration Scheme for Soft Real-time Constrained Embedded Systems
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
An Efficient Implementation Method of Arbiter for the ML-AHB Busmatrix
ICESS '07 Proceedings of the 3rd international conference on Embedded Software and Systems
The Lotterybus on-chip communication architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Latency-Guided On-Chip Bus-Network Design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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The multilayer advanced high-performance bus (ML-AHB) busmatrix employs slave-side arbitration. Slaveside arbitration is different from master-side arbitration in terms of request and grant signals since, in the former, the master merely starts a burst transaction and waits for the slave response to proceed to the next transfer. Therefore, in the former, the unit of arbitration can be a transaction or a transfer. However, the ML-AHB busmatrix of ARM offers only transfer-based fixed-priority and round-robin arbitration schemes. In this paper, we propose the design and implementation of a flexible arbiter for the ML-AHB busmatrix to support three priority policies--fixed priority, round robin, and dynamic priority--and three data multiplexing modes--transfer, transaction, and desired transfer length. In total, there are nine possible arbitration schemes. The proposed arbiter, which is self-motivated (SM), selects one of the nine possible arbitration schemes based upon the priority-level notifications and the desired transfer length from the masters so that arbitration leads to the maximum performance. Experimental results show that, although the area overhead of the proposed SM arbitration scheme is 9%-25% larger than those of the other arbitration schemes, our arbiter improves the throughput by 14%-62% compared to other schemes.