LOTTERYBUS: a new high-performance communication architecture for system-on-chip designs
Proceedings of the 38th annual Design Automation Conference
Efficient exploration of the SoC communication architecture design space
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
On-Chip Stochastic Communication
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
A continuous time markov decision process based on-chip buffer allocation methodology
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Stochastic modeling of a power-managed system-construction and optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Online adaptation policy design for grid sensor networks with reconfigurable embedded nodes
Proceedings of the Conference on Design, Automation and Test in Europe
Implementation of a self-motivated arbitration scheme for the multilayer ARB busmatrix
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents a stochastic approach for bus arbiter design. Arbiter design includes policy design, buffer insertion, and optimal buffer sizing. The methodology uses continuous-time Markov decision processes (CTMDPs) to get optimal arbitration policies and buffer space distribution. The mathematical formulation of this problem in terms of a CTMDP framework leads to a linear programming problem for bus architectures without bridges, and to a nonlinear formulation for bus architectures with bridges. In the second case, the methodology splits the nonlinear problem into several smaller, linear subsystems by introducing buffers at the bridges, and then solves the linear subsystems. In our experiments, we found that stochastic policies provide efficient arbitration for bus architectures with redundant buses for communication between processors. The size of buffers in some cases was reduced by 90%, and by 50% in the average sense. Data loss was reduced by 20% to 50% with redistribution of the buffer space.