Modern heuristic techniques for combinatorial problems
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Protocol selection and interface generation for HW-SW codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MOGAC: a multiobjective genetic algorithm for the co-synthesis of hardware-software embedded systems
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Communication synthesis for distributed embedded systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
COSYN: hardware-software co-synthesis of heterogeneous distributed embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Bus-based communication synthesis on system level
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Scheduling hardware/software systems using symbolic techniques
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
A low power hardware/software partitioning approach for core-based embedded systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Scheduling with bus access optimization for distributed embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
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Proceedings of the conference on Design, automation and test in Europe
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Proceedings of the 38th annual Design Automation Conference
Algorithms for VLSI Physcial Design Automation
Algorithms for VLSI Physcial Design Automation
Co-Synthesis of Hardware and Software for Digital Embedded Systems
Co-Synthesis of Hardware and Software for Digital Embedded Systems
Hardware-Software Co-Synthesis of Distributed Embedded Systems
Hardware-Software Co-Synthesis of Distributed Embedded Systems
Latency-guided on-chip bus network design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Efficient exploration of the SoC communication architecture design space
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
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IEEE Design & Test
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IEEE Design & Test
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IEEE Design & Test
System-Level Point-to-Point Communication Synthesis Using Floorplanning Information
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Scheduling Under Data and Control Dependencies for Heterogeneous Architectures
ICCD '98 Proceedings of the International Conference on Computer Design
Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip
Proceedings of the conference on Design, automation and test in Europe - Volume 1
Smart Sensor Architecture Customized for Image Processing Applications
RTAS '04 Proceedings of the 10th IEEE Real-Time and Embedded Technology and Applications Symposium
Issues and strategies for the physical design of system-on-a-chip ASICs
IBM Journal of Research and Development
Early analysis tools for system-on-a-chip design
IBM Journal of Research and Development
A global wiring paradigm for deep submicron design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Platune: a tuning framework for system-on-a-chip platforms
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Simultaneous synthesis of buses, data mapping and memory allocation for MPSoC
CODES+ISSS '07 Proceedings of the 5th IEEE/ACM international conference on Hardware/software codesign and system synthesis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A Systematic Design Space Exploration of MPSoC Based on Synchronous Data Flow Specification
Journal of Signal Processing Systems
Online adaptation policy design for grid sensor networks with reconfigurable embedded nodes
Proceedings of the Conference on Design, Automation and Test in Europe
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ACM Transactions on Embedded Computing Systems (TECS)
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This paper presents a layout-conscious approach for hardware/software codesign of systems-on-chip (SoCs) optimized for latency, including an original algorithm for bus architecture synthesis. Compared to similar work, the method addresses layout related issues that affect system optimization, such as the dependency of task communication speed on interconnect parasitic. The codesign flow executes three consecutive steps: 1) combined partitioning and scheduling: besides partitioning and scheduling, this step also identifies the minimum speed constraints for each data link; 2) IP core placement, bus architecture synthesis, and routing: IP cores are placed using a hierarchical cluster growth algorithm; bus architecture synthesis identifies a set of possible building blocks and then assembles them for minimizing bus length and complexity; poor solutions are pruned using a special table structure and select-eliminated method; and 3) rescheduling for the best bus architecture. This paper offers extensive experiments for the proposed codesign method, including bus architecture synthesis for a network processor and a JPEG SoC.