Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip

Authors:
Nattawut Thepayasuwan;Vaishali Damle;Alex Doboli
Affiliations:
-;-;-
Venue:
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Year:
2003

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Abstract

System level design always has a disadvantage of not possessingdetailed knowledge of the communication sub-system. This is acrucial issue for System-on-Chip design, where uncertainty incommunication by very deep submicron effects cannot be neglected.This paper presents a bus architecture (BA) synthesis algorithm fordesigning the communication sub-system of an SoC. The algorithm ispart of a hardware-software co-design methodology for resourceconstrained embedded applications. BA synthesis includes findingthe bus topology, and routing the individual buses so that variousconstraints, like bus length, topology complexity, potential forcommunication conflicts over time, are addressed. The paperpresents BA synthesis results for a network processor, and a JPEGSoC.