Protocol selection and interface generation for HW-SW codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Communication synthesis for distributed embedded systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Scheduling hardware/software systems using symbolic techniques
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Addressing the system-on-a-chip interconnect woes through communication-based design
Proceedings of the 38th annual Design Automation Conference
Co-Synthesis of Hardware and Software for Digital Embedded Systems
Co-Synthesis of Hardware and Software for Digital Embedded Systems
Hardware-Software Co-Synthesis of Distributed Embedded Systems
Hardware-Software Co-Synthesis of Distributed Embedded Systems
Scheduling for Embedded Real-Time Systems
IEEE Design & Test
Codesign of Embedded Systems: Status and Trends
IEEE Design & Test
Bus Architecture Synthesis for Hardware-Software Co-Design of Deep Submicron Systems on Chip
ICCD '03 Proceedings of the 21st International Conference on Computer Design
Early analysis tools for system-on-a-chip design
IBM Journal of Research and Development
System-level design: orthogonalization of concerns and platform-based design
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
System-level performance analysis for designing on-chip communication architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
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This paper presents a hardware-software co-design methodologyfor resource constrained SoC fabricated in a deep submicron process.The novelty of the methodology consists in contemplatingcritical hardware and layout aspects during system level designfor latency optimization. The effect of interconnect parasiticand delays is considered for characterizing bus speed anddata communication times. The methodology permits coarse andmedium grained resource sharing across tasks for execution speedupthrough superior usage of hardware. The paper offers experimentsfor the proposed co-design methodology, including a JPEG SoC.