Communication synthesis for distributed embedded systems

Interface synthesis: a vertical slice from digital logic to software components

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design

Multilanguage design of heterogeneous systems

CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign

ipChinook: an integrated IP-based design framework for distributed embedded systems

Proceedings of the 36th annual ACM/IEEE Design Automation Conference

A codesign virtual machine for hierarchical, balanced hardware/software system modeling

Proceedings of the 37th Annual Design Automation Conference

Communication architecture tuners: a methodology for the design of high-performance communication architectures for systems-on-chips

Proceedings of the 37th Annual Design Automation Conference

Bus access optimization for distributed embedded systems based on schedulability analysis

DATE '00 Proceedings of the conference on Design, automation and test in Europe

From high-level specifications down to software implementations of parallel embedded real-time systems

DATE '00 Proceedings of the conference on Design, automation and test in Europe

Modeling and evaluation of hardware/software designs

Proceedings of the ninth international symposium on Hardware/software codesign

Minimizing system modification in an incremental design approach

Proceedings of the ninth international symposium on Hardware/software codesign

An approach to incremental design of distributed embedded systems

Proceedings of the 38th annual Design Automation Conference

On-chip communication architecture for OC-768 network processors

Proceedings of the 38th annual Design Automation Conference

Modeling and simulation of steady state and transient behaviors for emergent SoCs

Proceedings of the 14th international symposium on Systems synthesis

Combined functional partitioning and communication speed selection for networked voltage-scalable processors

Proceedings of the 15th international symposium on System Synthesis

Efficient exploration of the SoC communication architecture design space

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design

An Interconnect Architecture for Networking Systems on Chips

IEEE Micro

Field Programmable Communication Emulation and Optimization for Embedded System Design

FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications

Optimization of Run-Time Reconfigurable Embedded Systems

FPL '00 Proceedings of the The Roadmap to Reconfigurable Computing, 10th International Workshop on Field-Programmable Logic and Applications

Communication speed selection for embedded systems with networked voltage-scalable processors

Proceedings of the tenth international symposium on Hardware/software codesign

A tool for describing and evaluating hierarchical real-time bus scheduling policies

Proceedings of the 40th annual Design Automation Conference

Multi-Level Communication Synthesis of Heterogeneous Multilanguage Specification

ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors

A fresh look at low-power mobile computing

Compilers and operating systems for low power

Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip

Proceedings of the conference on Design, automation and test in Europe - Volume 1

Schedulability-Driven Communication Synthesis for Time Triggered Embedded Systems

Real-Time Systems

Hardware-Software Co-Design of Resource Constrained Systems on a Chip

ICDCSW '04 Proceedings of the 24th International Conference on Distributed Computing Systems Workshops - W7: EC (ICDCSW'04) - Volume 7

Automatic generation of bus functional models from transaction level models

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Scheduling and Timing Analysis of HW/SW On-Chip Communication in MP SoC Design

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe: Designers' Forum - Volume 2

Scheduling and mapping in an incremental design methodology for distributed real-time embedded systems

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Methods for evaluating and covering the design space during early design development

Integration, the VLSI Journal

Performance aware on-chip communication synthesis and optimization for shared multi-bus based architecture

SBCCI '05 Proceedings of the 18th annual symposium on Integrated circuits and system design

Automatic network generation for system-on-chip communication design

CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis

Layout conscious approach and bus architecture synthesis for hardware/software codesign of systems on chip optimized for speed

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Schedule-aware performance estimation of communication architecture for efficient design space exploration

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Automated throughput-driven synthesis of bus-based communication architectures

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

System level design paradigms: Platform-based design and communication synthesis

Proceedings of the 41st annual Design Automation Conference

Automatic generation of transaction level models for rapid design space exploration

CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis

On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect

Applying stochastic modeling to bus arbitration for systems-on-chip

Integration, the VLSI Journal

Simultaneous on-chip bus synthesis and voltage scaling under random on-chip data traffic

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Wrapping of Soft IPs for Interface-based Design Using Heterogeneous Metaprogramming

Informatica

Dynamically configurable bus topologies for high-performance on-chip communication

IEEE Transactions on Very Large Scale Integration (VLSI) Systems