CoWare—a design environment for heterogenous hardware/software systems
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Hardware-software co-design of embedded systems: the POLIS approach
Hardware-software co-design of embedded systems: the POLIS approach
A geographically distributed framework for embedded system design and validation
DAC '98 Proceedings of the 35th annual Design Automation Conference
Optimistic distributed timed cosimulation based on thread simulation model
Proceedings of the 6th international workshop on Hardware/software codesign
Models and languages for parallel computation
ACM Computing Surveys (CSUR)
SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Hardware/software co-synthesis with memory hierarchies
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Communication synthesis for distributed embedded systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
The Verilog hardware description language (4th ed.)
The Verilog hardware description language (4th ed.)
Peer-based multithreaded executable co-specification
CODES '99 Proceedings of the seventh international workshop on Hardware/software codesign
Doing hard time: developing real-time systems with UML, objects, frameworks, and patterns
Doing hard time: developing real-time systems with UML, objects, frameworks, and patterns
Turning clockwise: using UML in the real-time domain
Communications of the ACM
Frequency interleaving as a codesign scheduling paradigm
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Frequency interleaving as a codesign scheduling paradigm
CODES '00 Proceedings of the eighth international workshop on Hardware/software codesign
Modeling and evaluation of hardware/software designs
Proceedings of the ninth international symposium on Hardware/software codesign
Modeling and simulation of steady state and transient behaviors for emergent SoCs
Proceedings of the 14th international symposium on Systems synthesis
Multi-Level Modeling of Software on Hardware in Concurrent Computation
IPDPS '02 Proceedings of the 16th International Parallel and Distributed Processing Symposium
Power-Performance Simulation and Design Strategies for Single-Chip Heterogeneous Multiprocessors
IEEE Transactions on Computers
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The Codesign Virtual Machine (CVM) is introduced as a next generation system modeling semantic. The CVM permits unrestricted system-wide software and hardware behaviors to be designed to a single scheduling semantic by resolving time-based (resource) and time-independent (state-interleaved) models of computation. CVM hierarchical relationships of bus and clock state domains provide a means of exploring hardware/software scheduling trade-offs to a consistent semantic model using top-down, bottom-up and iterative design approaches from a high system level to the machine implementation. State domain partitionings permit run-time software schedulers to be resolved with design time physical scheduling as peer- and hierarchically-related architectural abstractions which cut across functional boundaries. The resultant abstraction provides “component-less” paths to physical design with greater accommodation of shared resource modeling. A simulation example is included.