An architectural co-synthesis algorithm for distributed, embedded computing systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Communication synthesis for distributed embedded systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
FSMD functional partitioning for low power
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Scheduling with bus access optimization for distributed embedded systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on the 11th international symposium on system-level synthesis and design (ISSS'98)
Hybrid global/local search strategies for dynamic voltage scaling in embedded multiprocessors
Proceedings of the ninth international symposium on Hardware/software codesign
Battery-aware static scheduling for distributed real-time embedded systems
Proceedings of the 38th annual Design Automation Conference
Communication speed selection for embedded systems with networked voltage-scalable processors
Proceedings of the tenth international symposium on Hardware/software codesign
A low power based system partitioning and binding technique for multi-chip module architectures
GLS '97 Proceedings of the 7th Great Lakes Symposium on VLSI
Minimizing Energy Consumption for High-Performance Processing
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Energy efficient system partitioning for distributed wireless sensor networks
ICASSP '01 Proceedings of the Acoustics, Speech, and Signal Processing, 200. on IEEE International Conference - Volume 02
Integrating communication protocol selection with hardware/software codesign
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Novel Energy Saving Approach through Mobile Collaborative Computing Systems
International Journal of Handheld Computing Research
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This paper presents a new technique for global energy optimization through coordinated functional partitioning and speed selection for embedded processors interconnected by a high-speed serial bus. Many such serial interfaces are capable of operating at multiple speeds and can open up a new dimension of trade-offs to complement today's CPU-centric voltage scaling techniques for processors. We propose a multi-dimensional dynamic programming formulation for energy-optimal functional partitioning with CPU/communication speed selection for a class of data-regular applications under performance constraints. We demonstrate the effectiveness of our optimization techniques with an image processing application mapped onto a multi-processor architecture with a multi-speed Ethernet.