Sensitivity-driven co-synthesis of distributed embedded systems
ISSS '95 Proceedings of the 8th international symposium on System synthesis
Object-oriented cosynthesis of distributed embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
CORDS: hardware-software co-synthesis of reconfigurable real-time distributed embedded systems
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Hardware/software co-synthesis with memory hierarchies
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Application-specific heterogeneous multiprocessor synthesis using differential-evolution
Proceedings of the 11th international symposium on System synthesis
CMAPS: a cosynthesis methodology for application-oriented parallel systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System synthesis for multiprocessor embedded applications
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Allocation and scheduling of conditional task graph in hardware/software co-synthesis
Proceedings of the conference on Design, automation and test in Europe
Code placement in hardware/software co-synthesis to improve performance and reduce cost
Proceedings of the conference on Design, automation and test in Europe
Co-synthesis with custom ASICs
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
An approach to incremental design of distributed embedded systems
Proceedings of the 38th annual Design Automation Conference
Hardware/software co-synthesis with memory hierarchies
Readings in hardware/software co-design
Partitioning sequential programs for CAD using a three-step approach
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 15th international symposium on System Synthesis
Communication speed selection for embedded systems with networked voltage-scalable processors
Proceedings of the tenth international symposium on Hardware/software codesign
On the hardware-software partitioning problem: System modeling and partitioning techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Process Partitioning for Distributed Embedded Systems
CODES '96 Proceedings of the 4th International Workshop on Hardware/Software Co-Design
Iterative schedule optimization for voltage scalable distributed embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Algorithmic aspects of hardware/software partitioning
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Reliability-Centric Hardware/Software Co-Design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Configurable multi-processor architecture and its processor element design
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
System-level architectural exploration using allocation-on-demand technique
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Synthesis of an application-specific soft multiprocessor system
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
An architectural co-synthesis algorithm for energy-aware network-on-chip design
Proceedings of the 2007 ACM symposium on Applied computing
Finding optimal hardware/software partitions
Formal Methods in System Design
Variation-aware task allocation and scheduling for MPSoC
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Quality-driven model-based architecture synthesis for real-time embedded SoCs
Journal of Systems Architecture: the EUROMICRO Journal
Timing variation-aware task scheduling and binding for MPSoC
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
An architectural co-synthesis algorithm for energy-aware Network-on-Chip design
Journal of Systems Architecture: the EUROMICRO Journal
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
Synthesis algorithm for application-specific homogeneous processor networks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evaluating the Kernighan-Lin Heuristic for Hardware/Software Partitioning
International Journal of Applied Mathematics and Computer Science
On-chip bus architecture optimization for multi-core SoC systems
SEUS'07 Proceedings of the 5th IFIP WG 10.2 international conference on Software technologies for embedded and ubiquitous systems
System synthesis and processor selection in the S3E2S environment
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Efficient genetic based topological mapping using analytical models for on-chip networks
Journal of Computer and System Sciences
On robust task-accurate performance estimation
Proceedings of the 50th Annual Design Automation Conference
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Many embedded computers are distributed systems, composed of several heterogeneous processors and communication links of varying speeds and topologies. This paper describes a new, heuristic algorithm which simultaneously synthesizes the hardware and software architectures of a distributed system to meet a performance goal and minimize cost. The hardware architecture of the synthesized system consists of a network of processors of multiple types and arbitrary communication topology; the software architecture consists of an allocation of processes to processors and a schedule for the processes. Most previous work in co-synthesis targets an architectural template, whereas this algorithm can synthesize a distributed system of arbitrary topology. The algorithm works from a technology database which describes the available processors, communication links, I/O devices, and implementations of processes on processors. Previous work had proposed solving this problem by integer linear programming (ILP); our algorithm is much faster than ILP and produces high-quality results.