On-chip bus architecture optimization for multi-core SoC systems

Authors:
Cheng-Min Lien;Ya-Shu Chen;Chi-Sheng Shih
Affiliations:
Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan;Department of Computer Science and Information Engineering, National Taiwan University, Taipei, Taiwan;Graduate Institute of Networking and Multimedia, National Taiwan University, Taipei, Taiwan
Venue:
SEUS'07 Proceedings of the 5th IFIP WG 10.2 international conference on Software technologies for embedded and ubiquitous systems
Year:
2007

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Abstract

With the significant driving force from the application domains, modern embedded systems are designed over heterogeneous multicore SoC platforms. When more and more functions are integrated into one system, the designs of embedded systems have become more and more complicated. In particular, most of embedded multimedia applications are data intensive. Performance bottleneck are often caused by inappropriate bus architecture design within the system. In this paper, we present the algorithms for bus architecture optimization in MFASE. The algorithm takes the workloads in the system and their timing behavior requirements into account. The goal is to minimize the number of buses in the system without violating timing requirements. We prove that the minimzation problem is NP-hard and develop a heuristic algorithm. We evaluate the algorithm with extensive simulations. The performance results show that the algorithm reduce up to 80% of the bus cost and performs as well as optimal exponential algorithm does.