REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Optimum and heuristic data path scheduling under resource constraints
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
The combination of scheduling, allocation, and mapping in a single algorithm
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A generalized interconnect model for data path synthesis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Data path tradeoffs using MABAL
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Constraint improvements for MILP-based hardware synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Comprehensive lower bound estimation from behavioral descriptions
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming
EURO-DAC '94 Proceedings of the conference on European design automation
Synthesis of signal processing structured datapaths for FPGAs supporting RAMs and busses
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Statistical performance-driven module binding in high-level synthesis
Proceedings of the 11th international symposium on System synthesis
Register binding and port assignment for multiplexer optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Platform-based resource binding using a distributed register-file microarchitecture
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Compatibility path based binding algorithm for interconnect reduction in high level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Simultaneous FU and register binding based on network flow method
Proceedings of the conference on Design, automation and test in Europe
A Behavioral Synthesis Method with Special Functional Units
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
Better than optimum?: register reduction using idle pipelined functional units
Proceedings of the 19th ACM Great Lakes symposium on VLSI
On-chip bus architecture optimization for multi-core SoC systems
SEUS'07 Proceedings of the 5th IFIP WG 10.2 international conference on Software technologies for embedded and ubiquitous systems
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