Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Scheduling and binding algorithms for high-level synthesis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Loop optimization in register-transfer scheduling for DSP-systems
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
A method of automatic data path synthesis
DAC '83 Proceedings of the 20th Design Automation Conference
A formal method for the specification, analysis, and design of register-transfer level digital logic
DAC '81 Proceedings of the 18th Design Automation Conference
Optimal allocation and binding in high-level synthesis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Move frame scheduling and mixed scheduling-allocation for the automated synthesis of digital systems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Synthesis of application-specific multiprocessor architectures
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Constraint improvements for MILP-based hardware synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Datapath scheduling for two-level pipelining
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Scheduling for functional pipelining and loop winding
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
A neural network based algorithm for the scheduling problem in high-level synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Optimization and resynthesis of complex data-paths
DAC '93 Proceedings of the 30th international Design Automation Conference
Incorporating speculative execution in exact control-dependent scheduling
DAC '94 Proceedings of the 31st annual Design Automation Conference
Automatic synthesis of a dual-PLA controller with a counter
MICRO 23 Proceedings of the 23rd annual workshop and symposium on Microprogramming and microarchitecture
A unified approach for scheduling and allocation
Integration, the VLSI Journal
Optimal and heuristic algorithms for solving the binding problem
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper presents an integer linear programming model for the scheduling problem in high level synthesis under resource constraints. Extensive consideration is given to the following applications:Multi-cycle operations withnon-pipelined function units,pipelined function units;Mutually exclusive operations;Functional pipelining;Loop folding;Scheduling under bus constraint.Using this model, we are able to solve all the benchmarks in the literature optimally in a few seconds. Besides the model, a new technique, called Zone Scheduling (ZS), is proposed to solve large size problems. ZS partitions the distribution graph into several zones and solves sequentially the problems contained. A novel feature of this technique is that it schedules more than one control step at a time, allowing us to take a more global view of a scheduling problem.