Optimal allocation and binding in high-level synthesis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Data path allocation based on bipartite weighted matching
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
High-level synthesis: introduction to chip and system design
High-level synthesis: introduction to chip and system design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Integration, the VLSI Journal
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Low-energy embedded FPGA structures
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Splicer: a heuristic approach to connectivity binding
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Theoretical Improvements in Algorithmic Efficiency for Network Flow Problems
Journal of the ACM (JACM)
Efficient circuit clustering for area and power reduction in FPGAs
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Synthesis and Optimization of Digital Circuits
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Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
Low-power high-level synthesis for FPGA architectures
Proceedings of the 2003 international symposium on Low power electronics and design
Elements of discrete mathematics (McGraw-Hill computer science series)
Elements of discrete mathematics (McGraw-Hill computer science series)
Instruction set extension with shadow registers for configurable processors
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Optimal module and voltage assignment for low-power
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Optimal simultaneous module and multivoltage assignment for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Register binding for clock period minimization
Proceedings of the 43rd annual Design Automation Conference
Interference graphs for procedures in static single information form are interval graphs
SCOPES '07 Proceedingsof the 10th international workshop on Software & compilers for embedded systems
Early planning for clock skew scheduling during register binding
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Compatibility path based binding algorithm for interconnect reduction in high level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Simultaneous FU and register binding based on network flow method
Proceedings of the conference on Design, automation and test in Europe
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Better than optimum?: register reduction using idle pipelined functional units
Proceedings of the 19th ACM Great Lakes symposium on VLSI
FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation
Proceedings of the 46th Annual Design Automation Conference
Minimum-period register binding
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A functional unit and register binding algorithm for interconnect reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
HLS-l: a high-level synthesis framework for latch-based architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coordinated resource optimization in behavioral synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
A global interconnect reduction technique during high level synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Towards layout-friendly high-level synthesis
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A metric for layout-friendly microarchitecture optimization in high-level synthesis
Proceedings of the 49th Annual Design Automation Conference
Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
A heuristic scheduler for port-constrained floating-point pipelines
International Journal of Reconfigurable Computing
FPGA latency optimization using system-level transformations and DFG restructuring
Proceedings of the Conference on Design, Automation and Test in Europe
Scheduling independent liveness analysis for register binding in high level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
HLS-dv: a high-level synthesis framework for dual-Vdd architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors
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Data path connection elements, such as multiplexers, consume a significant amount of area on a VLSI chip, especially for FPGA designs. Multiplexer optimization is a difficult problem because both register binding and port assignment to reduce total multiplexer connectivity during high-level synthesis are NP-complete problems. In this paper, we first formulate a k-cofamily-based register binding algorithm targeting the multiplexer optimization problem. We then further reduce the multiplexer width through an efficient port assignment algorithm. Experimental results show that we are 44% better overall than the left-edge register binding algorithm on the total usage of multiplexer inputs and 7% better than a bipartite graph-based algorithm. For large designs, we are able to achieve significantly better results consistently. After technology mapping, placement and routing for an FPGA architecture, it shows considerably positive impacts on chip area, delay and power consumption.