Combinatorial optimization: algorithms and complexity
Combinatorial optimization: algorithms and complexity
REAL: a program for REgister ALlocation
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Tutorial on high-level synthesis
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Splicer: a heuristic approach to connectivity binding
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
A new synthesis for the MIMOLA software system
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Sehwa: a program for synthesis of pipelines
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
MAHA: a program for datapath synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
Wire routing by optimizing channel assignment within large apertures
DAC '71 Proceedings of the 8th Design Automation Workshop
Combinatorial Algorithms: Theory and Practice
Combinatorial Algorithms: Theory and Practice
Relevant issues in high-level connectivity synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Data path allocation using an extended binding model
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
DAC '93 Proceedings of the 30th international Design Automation Conference
Utilization of multiport memories in data path synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
Recent developments in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Code generation for a DSP processor
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Statistical performance-driven module binding in high-level synthesis
Proceedings of the 11th international symposium on System synthesis
Register Allocation—A Hierarchical Reduction Approach
Journal of VLSI Signal Processing Systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Data and memory optimization techniques for embedded systems
ACM Transactions on Design Automation of Electronic Systems (TODAES)
ACM Transactions on Design Automation of Electronic Systems (TODAES)
High-level synthesis of multiple-precision circuits independent of data-objects length
Proceedings of the 39th annual Design Automation Conference
Protocol selection and interface generation for HW-SW codesign
Readings in hardware/software co-design
Bit-level scheduling of heterogeneous behavioural specifications
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A Hierarchical Register Optimization Algorithm for Behavioral Synthesis
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
Low-power high-level synthesis for FPGA architectures
Proceedings of the 2003 international symposium on Low power electronics and design
SymSim: Symbolic Fault Simulation of Data- ow Data-path Designs at the Register-Transfer Level
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Register binding and port assignment for multiplexer optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Synthesis of Application-Specific Highly-Efficient Multi-Mode Systems for Low-Power Applications
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
High-Level Allocation to Minimize Internal Hardware Wastage
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Synthesis of application-specific highly efficient multi-mode cores for embedded systems
ACM Transactions on Embedded Computing Systems (TECS)
Highly flexible multi-mode system synthesis
CODES+ISSS '05 Proceedings of the 3rd IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
Platform-based resource binding using a distributed register-file microarchitecture
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Compatibility path based binding algorithm for interconnect reduction in high level synthesis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
A design flow dedicated to multi-mode architectures for DSP applications
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Pattern-based behavior synthesis for FPGA resource reduction
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
Behavioral synthesis with activating unused flip-flops for reducing glitch power in FPGA
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Simultaneous FU and register binding based on network flow method
Proceedings of the conference on Design, automation and test in Europe
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Area optimisation for field-programmable gate arrays in SystemC hardware compilation
International Journal of Reconfigurable Computing - Selected Papers from SPL 2008: Programmable Logic and Applications
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Better than optimum?: register reduction using idle pipelined functional units
Proceedings of the 19th ACM Great Lakes symposium on VLSI
FPGA-targeted high-level binding algorithm for power and area reduction with glitch-estimation
Proceedings of the 46th Annual Design Automation Conference
High-level synthesis for the design of FPGA-based signal processing systems
SAMOS'09 Proceedings of the 9th international conference on Systems, architectures, modeling and simulation
A functional unit and register binding algorithm for interconnect reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coordinated resource optimization in behavioral synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
A global interconnect reduction technique during high level synthesis
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
High-level synthesis for designing multimode architectures
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Incremental synthesis of application domain specific processors
ICASSP'93 Proceedings of the 1993 IEEE international conference on Acoustics, speech, and signal processing: plenary, special, audio, underwater acoustics, VLSI, neural networks - Volume I
LegUp: high-level synthesis for FPGA-based processor/accelerator systems
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Word-Length Aware DSP Hardware Design Flow Based on High-Level Synthesis
Journal of Signal Processing Systems
Design of multi-mode application-specific cores based on high-level synthesis
Integration, the VLSI Journal
Fast algorithms for weighted bipartite matching
WEA'05 Proceedings of the 4th international conference on Experimental and Efficient Algorithms
Towards layout-friendly high-level synthesis
Proceedings of the 2012 ACM international symposium on International Symposium on Physical Design
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
A metric for layout-friendly microarchitecture optimization in high-level synthesis
Proceedings of the 49th Annual Design Automation Conference
A heuristic scheduler for port-constrained floating-point pipelines
International Journal of Reconfigurable Computing
Multi-pumping for resource reduction in FPGA high-level synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems
ACM Transactions on Embedded Computing Systems (TECS) - Special issue on application-specific processors
From software to accelerators with LegUp high-level synthesis
Proceedings of the 2013 International Conference on Compilers, Architectures and Synthesis for Embedded Systems
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We propose a graph-theoretic approach for the data path allocation problem. We decompose the problem into three subproblems: (1) register allocation, (2) operation assignment, and (3) connection allocation. The first two subproblems are modeled as two bipartite weighted matching problems and solved using the Hungarian Method [Pap82]. The third subproblem is solved using a greedy method. While previous researches suffer controversy over which one of subproblems (1) and (2) should be done first, we show that, by taking the other into consideration while performing one, equally satisfactory results can be obtained. We have implemented two programs, LYRA and ARYL, to solve the subproblems in different orders, namely, “(1), (2), then (3)” and “(2), (1), then (3)”, respectively. The matching paradigm allows us to take a more global approach toward the problem than previous researches do. For register allocation, our approach is the first one to guarantee minimal usage of registers while being able to take the interconnection cost into account. For all the benchmarks from the literature, both LYRA and ARYL produced designs as good as, if not better than, those by others in very short time. This research has demonstrated that the bipartite weighted matching algorithm is indeed a very good solution for the data path allocation problem.