Data path allocation based on bipartite weighted matching
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Data path tradeoffs using MABAL
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A methodology and design environment for DSP ASIC fixed point refinement
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Low-power behavioral synthesis optimization using multiple precision arithmetic
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Heuristic datapath allocation for multiple wordlength systems
Proceedings of the conference on Design, automation and test in Europe
High-Performance Digit-Serial Complex-Number Multiplier-Accumulator
ICCD '98 Proceedings of the International Conference on Computer Design
Multiple-Precision Circuits Allocation Independent of Data-Objects Length
Proceedings of the conference on Design, automation and test in Europe
Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
Behavioural Bitwise Scheduling Based on Computational Effort Balancing
Proceedings of the conference on Design, automation and test in Europe - Volume 1
High-Level Allocation to Minimize Internal Hardware Wastage
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Arrival time aware scheduling to minimize clock cycle length
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Pre-synthesis optimization of multiplications to improve circuit performance
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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This paper presents a heuristic scheduling algorithm for heterogeneous specifications, those formed by operations of different types and widths. The algorithm extracts the common operative kernel of the operations, and binds afterwards operations to cycles with the aim of distributing uniformly the number of bits calculated per cycle. In consequence, operations may be fragmented and executed during a set of non-necessarily consecutive cycles, and over a set of several linked simple hardware resources. The proposed algorithm, in combination with allocation algorithms able to guarantee bit-level reuse of hardware resources, obtains considerably smaller datapaths than the ones proposed by conventional synthesis algorithms. In the datapaths produced the type, number, and width of the hardware resources are independent of the type, number, and width of the specification operations and variables.