High-level synthesis of multiple-precision circuits independent of data-objects length
Proceedings of the 39th annual Design Automation Conference
Bit-level scheduling of heterogeneous behavioural specifications
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
High-Level Allocation to Minimize Internal Hardware Wastage
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Optimum and heuristic synthesis of multiple word-length architectures
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Arrival time aware scheduling to minimize clock cycle length
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
| Hi-index | 0.00 |
This paper presents an heuristic method to solve thecombined resource selection and binding problems for thehigh-level synthesis of multiple-precision specifications.Traditionally, the number of functional (and storage)units in a datapath is determined by the maximum numberof operations scheduled in the same cycle, with theirrespective widths depending on the number of bits of thewider operations. When these wider operations are notscheduled in such "busy" cycle, this way of acting couldproduce a considerable waste of area.To overcome this problem, we propose the selection ofthe set of resources taking into account the only trulyrelevant aspect: the maximum number of bits calculatedand stored simultaneously in a cycle. The implementationobtained is a multiple-precision datapath, where thenumber and widths of the resources are independent ofthe specification operations and data objects.