Data path allocation based on bipartite weighted matching
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Data path tradeoffs using MABAL
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
OSCAR: optimum simultaneous scheduling, allocation and resource binding based on integer programming
EURO-DAC '94 Proceedings of the conference on European design automation
System level fixed-point design based on an interpolative approach
DAC '97 Proceedings of the 34th annual Design Automation Conference
A methodology and design environment for DSP ASIC fixed point refinement
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Low-power behavioral synthesis optimization using multiple precision arithmetic
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Precision and error analysis of MATLAB applications during automated hardware synthesis for FPGAs
Proceedings of the conference on Design, automation and test in Europe
Heuristic datapath allocation for multiple wordlength systems
Proceedings of the conference on Design, automation and test in Europe
High-level synthesis of multiple-precision circuits independent of data-objects length
Proceedings of the 39th annual Design Automation Conference
Bit-level scheduling of heterogeneous behavioural specifications
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Multiple Precision for Resource Minimization
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
Formal Techniques for Hardware Allocation
VLSID '97 Proceedings of the Tenth International Conference on VLSI Design: VLSI in Multimedia Applications
High-Level Allocation to Minimize Internal Hardware Wastage
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Performance-driven scheduling of behavioural specifications
Integration, the VLSI Journal
Frequent-pattern-guided multilevel decomposition of behavioral specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper proposes an allocation algorithm able to perform the combined resource selection and operation binding of multiple precision specifications. The common operative kernel of additive specification operations is extracted, and an allocation independent of the operations widths is performed. As a result, one operation may be executed over either one wider functional unit, or a set of linked narrower functional units. This allocation approach maximizes the bit level reuse of hardware resources, thus substantially reducing the area of the final implementations. The maximum number of bits computed per cycle becomes the sole determining factor affecting the cost of circuits, in contrast with circuits proposed by conventional algorithms which are influenced by the number and widths of the operations executed in every cycle.Additionally an analytical method is presented to estimate the amount of area potentially saved in comparison with conventional allocation algorithms.