Soft scheduling in high level synthesis
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Low-power behavioral synthesis optimization using multiple precision arithmetic
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The use of carry-save representation in joint module selection and retiming
Proceedings of the 37th Annual Design Automation Conference
Power minimization of functional units partially guarded computation
ISLPED '00 Proceedings of the 2000 international symposium on Low power electronics and design
High-level synthesis under multi-cycle interconnect delay
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Coordinated transformations for high-level synthesis of high performance microprocessor blocks
Proceedings of the 39th annual Design Automation Conference
Efficient scheduling of conditional behaviors for high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Allocation of multiple precision behaviors for maximal bit level reuse of hardware resources
Journal of Systems Architecture: the EUROMICRO Journal - Special issue: Synthesis and verification
A scheduling algorithm for optimization and early planning in high-level synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Behavioural Transformation to Improve Circuit Performance in High-Level Synthesis
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
Force-directed scheduling for the behavioral synthesis of ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sehwa: a software package for synthesis of pipelines from behavioral specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Integrating variable-latency components into high-level synthesis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Performance-driven high-level synthesis with bit-level chaining and clock selection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Bitwise scheduling to balance the computational cost of behavioral specifications
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Conventional scheduling algorithms usually adjust the clock cycle duration to the execution time of the longest operations. This results in large slack times wasted in those cycles with faster operations. To reduce the wasted times multi-cycle and chaining techniques have been employed. Chaining contributes to reduce the circuit latency if it is applied to the critical path operations, and multi-cycle operators usually result in smaller clock cycles. Both techniques are applied at the operation level, and thus their impact on the circuit performance is bounded by the selected latency. Additionally, they have limited reusability. The design methodology presented in this paper overcomes the limitations of previous techniques to obtain substantially faster circuits. It fragments some of the specification operations into several smaller ones that are handled independently. This way, some operations can begin before their predecessors have finished and can also be executed in several unconsecutive cycles. Furthermore, the fragmentation of operations favours the reusability of hardware resources, leading also to smaller designs.