CODES '94 Proceedings of the 3rd international workshop on Hardware/software co-design
High level synthesis: a data path partitioning method dedicated to speed enhancement
EURO-DAC '91 Proceedings of the conference on European design automation
Journal of Parallel and Distributed Computing
Resource-constrained loop scheduling in high-level synthesis
Proceedings of the 43rd annual Southeast regional conference - Volume 2
Journal of Parallel and Distributed Computing
Performance-driven scheduling of behavioural specifications
Integration, the VLSI Journal
High level synthesis of integrated heterogeneous pipelined processing elements for DSP applications
Computers and Electrical Engineering
Modern development methods and tools for embedded reconfigurable systems: A survey
Integration, the VLSI Journal
A unified approach for scheduling and allocation
Integration, the VLSI Journal
A Force-Directed Scheduling based architecture generation algorithm and design tool for FPGAs
Journal of Systems Architecture: the EUROMICRO Journal
Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special section on adaptive power management for energy and temperature-aware computing systems
A fragmentation aware High-Level Synthesis flow for low power heterogenous datapaths
Integration, the VLSI Journal
Translation validation of scheduling in high level synthesis
Proceedings of the 23rd ACM international conference on Great lakes symposium on VLSI
A heuristic scheduler for port-constrained floating-point pipelines
International Journal of Reconfigurable Computing
Proceedings of the Conference on Design, Automation and Test in Europe
Modeling and simulation in a formal design framework
Proceedings of the 6th Balkan Conference in Informatics
Partial online-synthesis for mixed-grained reconfigurable architectures
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis
SDC-based modulo scheduling for pipeline synthesis
Proceedings of the International Conference on Computer-Aided Design
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A general scheduling methodology is presented that can be integrated into specialized or general-purpose high-level synthesis systems. An initial version of the force-directed scheduling algorithm at the heart of this methodology was originally presented by the authors in 1987. The latest implementation of the logarithm introduced here reduces the number of functional units, storage units, and buses required by balancing the concurrency of operations assigned to them. The algorithm supports a comprehensive set of constraint types and scheduling modes. These include multicycle and chained operations; mutually exclusive operations; scheduling under fixed global timing constraints with minimization of functional unit costs, minimization of register costs, and minimization of global interconnect requirements; scheduling with local time constraints (on operation pairs); scheduling under fixed hardware resource constraints; functional pipelining; and structural pipeline (use of pipeline functional units). Examples from current literature, one of which was chosen as a benchmark for the 1988 High-Level Synthesis Workshop, are used to illustrate the effectiveness of the approach