Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Verified high-level synthesis
Formulation and evaluation of scheduling techniques for control flow graphs
EURO-DAC '95/EURO-VHDL '95 Proceedings of the conference on European design automation
Optimal weighted loop fusion for parallel programs
Proceedings of the ninth annual ACM symposium on Parallel algorithms and architectures
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Probabilistic Loop Scheduling for Applications with Uncertain Execution Time
IEEE Transactions on Computers
Algorithms for High-Level Synthesis
IEEE Design & Test
Force-directed scheduling for the behavioral synthesis of ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Today electronic design automation software plays an important role in modern VLSI design technology. High-Level Synthesis (HLS) translates the behavioral specification of a digital system to a register transfer level structure. In this research we will focus scheduling loop constructs under fixed hardware constraints. We proposed a new two-phase algorithm for loop scheduling based on the Force-Directed Scheduling (FDS) algorithm. The algorithm also employs a local priority function called the 'mobility' of an operation to select the best operation to be rescheduled when resource violation is detected. In the first phase of the algorithm, the FDS algorithm is used to generate an initial schedule of the system that balances the distribution of the operations and optimizes the system hardware utilization. The second phase of the algorithm iteratively modifies the initial FDS schedule in order to resolve any hardware constraint violations. The performance of the proposed algorithm was evaluated using the differential equation and elliptical wave filter HLS benchmarks. The algorithm was found to significantly reduce the execution time under relaxed hardware constraints and yield results similar to the traditional sequential scheduler under tight hardware constraints.