LISP
Facet: A procedure for the automated synthesis of digital systems
DAC '83 Proceedings of the 20th Design Automation Conference
Bristle Blocks: A silicon compiler
DAC '79 Proceedings of the 16th Design Automation Conference
Combinatorial Algorithms: Theory and Practice
Combinatorial Algorithms: Theory and Practice
Simula Begin
Force-directed scheduling in automatic data path synthesis
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Knowledge based control in micro-architecture design
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
STEM: an IC design environment based on the Smalltalk model-view-controller construct
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Scheduling and binding algorithms for high-level synthesis
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Integrated scheduling and binding: a synthesis approach for design space exploration
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A technology-adaptive allocation of functional units and connections
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
VHDL synthesis using structured modeling
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
Relative scheduling under timing constraints
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Data path allocation based on bipartite weighted matching
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A global, dynamic register allocation and binding for a data path synthesis system
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Relevant issues in high-level connectivity synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Fast and near optimal scheduling in automatic data path synthesis
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Data path allocation using an extended binding model
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Superpipelined control and data path synthesis
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
System clock estimation based on clock slack minimization
EURO-DAC '92 Proceedings of the conference on European design automation
Flexible controlpath microarchitecture synthesis based on artificial intelligence
EURO-DAC '92 Proceedings of the conference on European design automation
Performance-driven interconnection optimization for microarchitecture synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
DAC '93 Proceedings of the 30th international Design Automation Conference
Information theoretic measures of energy consumption at register transfer level
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
An optimal clock period selection method based on slack minimization criteria
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A hardware/software partitioning algorithm for designing pipelined ASIPs with least gate counts
DAC '96 Proceedings of the 33rd annual Design Automation Conference
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Rapid performance estimation for system design
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Bridge: a versatile behavioral synthesis system
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Behavioral synthesis for easy testability in data path scheduling
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Accounting for various register allocation schemes during post-synthesis verification of RTL designs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Incremental Testability Analysis for Partial Scan Selection and Design Transformations
Journal of Electronic Testing: Theory and Applications - Special issue on the IEEE European Test Workshop
A flexible datapath allocation method for architectural synthesis
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Fast and accurate estimation of floorplans in logic/high-level synthesis
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
An efficient algorithm to integrated scheduling and allocation in high-level test synthesis
Proceedings of the conference on Design, automation and test in Europe
Automated Correctness Condition Generation for Formal Verification ofSynthesized RTL Designs
Formal Methods in System Design - Special issue on formal methods for computer-added design
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Cost/Quality Trade-off in Synthesis for BIST
Journal of Electronic Testing: Theory and Applications
Cycle-time aware architecture synthesis of custom hardware accelerators
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
Algorithms for High-Level Synthesis
IEEE Design & Test
An Optimizer for Hardware Synthesis
IEEE Design & Test
Specification, Planning, and Synthesis in a VHDL Design Environment
IEEE Design & Test
Contribution of Compilation Techniques to the Synthesis of Dedicated VLIW Architectures
PACT '93 Proceedings of the IFIP WG10.3. Working Conference on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism
Partial Scan High-Level Synthesis
EDTC '96 Proceedings of the 1996 European conference on Design and Test
MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
A Hierarchical Register Optimization Algorithm for Behavioral Synthesis
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
A Heuristic for Clock Selection in High-Level Synthesis
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
SymSim: Symbolic Fault Simulation of Data- ow Data-path Designs at the Register-Transfer Level
ITC '99 Proceedings of the 1999 IEEE International Test Conference
EURO-DAC '90 Proceedings of the conference on European design automation
EURO-DAC '90 Proceedings of the conference on European design automation
Open-ended system for high-level synthesis of flexible signal processors
EURO-DAC '90 Proceedings of the conference on European design automation
A design representation for high level synthesis
EURO-DAC '90 Proceedings of the conference on European design automation
High level synthesis: a data path partitioning method dedicated to speed enhancement
EURO-DAC '91 Proceedings of the conference on European design automation
Datapath optimization using feedback
EURO-DAC '91 Proceedings of the conference on European design automation
Optimization of micro-controllers by partitioning
EURO-DAC '91 Proceedings of the conference on European design automation
Register binding and port assignment for multiplexer optimization
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Scalable interprocedural register allocation for high level synthesis
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
A parameterized graph-based framework for high-level test synthesis
Integration, the VLSI Journal
Resource-constrained loop scheduling in high-level synthesis
Proceedings of the 43rd annual Southeast regional conference - Volume 2
Co-evolutionary high-level test synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Testability analysis based on the identification of testable blocks with predefined properties
Microprocessors & Microsystems
Simultaneous FU and register binding based on network flow method
Proceedings of the conference on Design, automation and test in Europe
Optimal synthesis of control logic from behavioral specifications
Integration, the VLSI Journal
Design for testability reuse in synthesis for testability
SBCCI'99 Proceedings of the XIIth conference on Integrated circuits and systems design
Coordinated resource optimization in behavioral synthesis
Proceedings of the Conference on Design, Automation and Test in Europe
A cyclic scheduling problem with an undetermined number of parallel identical processors
Computational Optimization and Applications
Mathematical and Computer Modelling: An International Journal
Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
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A novel approach to automatic data path synthesis is presented. This approach features innovations in the synthesis process as well as in the system implementation.The synthesis process exhibits three new features. The first relates to a subtask that performs an expert analysis of the input data flow graph and attempts to evenly distribute operations requiring similar resources. This is done using a novel “load balancing” technique. The second consists of a global preselection of operator cells to fulfill an explicit speed constraint. Finally, the third deals with new techniques for register and multiplexer optimization. These features support extended design space search by taking an explicit performance specification into account.The system implementation is based on the LOOPS multiparadigm programming system. In this approach the overall task can be partitioned into complementary subtasks requiring different programming paradigms. These subtasks will be realized using an object-based paradigm, a knowledge-based expert system paradigm, a functional paradigm, or combinations of all three.Two complete examples are given to demonstrate the functionality of the system and to allow comparison with existing systems.