Test Schedules for VLSI Circuits Having Built-In Test Hardware
IEEE Transactions on Computers - The MIT Press scientific computation series
A hierarchical test generation methodology for digital circuits
Journal of Electronic Testing: Theory and Applications
Data path allocation based on bipartite weighted matching
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Sequential test generation at the register-transfer and logic levels
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Hierarchical test generation under intensive global functional constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
DAC '93 Proceedings of the 30th international Design Automation Conference
Merging multiple FSM controllers for DFT/BIST hardware
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
High level test generation using data flow descriptions
EURO-DAC '90 Proceedings of the conference on European design automation
SymSim: Symbolic Fault Simulation of Data- ow Data-path Designs at the Register-Transfer Level
ITC '99 Proceedings of the 1999 IEEE International Test Conference
| Hi-index | 0.00 |
In this paper we discuss a new automatic test scheduling system for architectures that use separate control and data-paths. MUlti-STage-Combinational Testing (MUSTC-Testing) at the Register-Transfer Level significantly eases test generation and can be used in lieu of or to complement sequential test generation at the gate level. We provide a system with eleven signal types to perform test scheduling at the RT level which allows module level pre-computed test sets to be directly used for testing. A test scheduler is then described along with the results obtained.