Data path allocation based on bipartite weighted matching
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Sequential test generation at the register-transfer and logic levels
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
DAC '93 Proceedings of the 30th international Design Automation Conference
Merging multiple FSM controllers for DFT/BIST hardware
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Data Structures and Algorithms
Data Structures and Algorithms
A new architectural-level fault simulation using propagation prediction of grouped fault-effects
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
Register-transfer level test generation and test synthesis strategies for data-flow data-paths
Register-transfer level test generation and test synthesis strategies for data-flow data-paths
HITEC: a test generation package for sequential circuits
EURO-DAC '91 Proceedings of the conference on European design automation
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This paper presents a technique and tool (Sym-Sim) for symbolic fault-simulation of data-pathsspecified at the Register-Transfer Level (RTL) constrained by specific control sequences. SymSimachieves this using a symbolic value system suitablefor RTL simulation. It also computes and maintainsinput dependency information at each node in thedesign using a novel artifact called Dependency Setwhich at any time-frame contains all primary inputsymbols that effect the current value on that node.Symbolic fault-simulation can be used along with asymbolic test-generator to detect multiple faults witha single test to reduce test length and and generationtime.