A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Data path allocation based on bipartite weighted matching
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
A data path synthesis method for self-testable designs
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Splicer: a heuristic approach to connectivity binding
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Behavioral synthesis for easy testability in data path scheduling
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
VLSI and Modern Signal Processing
VLSI and Modern Signal Processing
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Behavioral Synthesis for Easy Testability in Data Path Allocation
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Non-scan design-for-testability of RT-level data paths
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Optimizing resource utilization and testability using hot potato techniques
DAC '94 Proceedings of the 31st annual Design Automation Conference
Data path allocation for synthesizing RTL design with low BIST area overhead
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Test register insertion with minimum hardware cost
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
A controller-based design-for-testability technique for controller-data path circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
High-level synthesis for testability: a survey and perspective
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Concurrent testing in high-level synthesis
ISSS '94 Proceedings of the 7th international symposium on High-level synthesis
Exploiting hardware sharing in high-level synthesis for partial scan optimization
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
An improved method for RTL synthesis with testability tradeoffs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Behavioral Testability Insertion for Datapath/Controller Circuits
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
Improving Testability of Non-Scan Designs during BehavioralSynthesis
Journal of Electronic Testing: Theory and Applications - Special issue on test synthesis
High-level variable selection for partial-scan implementation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Design for Testability Techniques at the Behavioraland Register-Transfer Levels
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
High-Level Controllability and Observability Analysis for Test Synthesis
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
High-Level Test Synthesis for Behavioral and Structural Designs
Journal of Electronic Testing: Theory and Applications - special issue on high-level test synthesis
Formal Value-Range and Variable Testability Techniquesfor High-Level Design-For-Testability
Journal of Electronic Testing: Theory and Applications - Special issue on microprocessor test and verification
Behavioral-Level DFT via Formal Operator Testability Measures
Journal of Electronic Testing: Theory and Applications
Test session oriented built-in self-testable data path synthesis
ITC '98 Proceedings of the 1998 IEEE International Test Conference
Partial Scan High-Level Synthesis
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Structural BIST Insertion Using Behavioral Test Analysis
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Analyzing Testability from Behavioral to RT Level
EDTC '97 Proceedings of the 1997 European conference on Design and Test
An RTL Methodology to Enable Low Overhead Combinational Testing
EDTC '97 Proceedings of the 1997 European conference on Design and Test
A Controller Testability Analysis and Enhancement Technique
EDTC '97 Proceedings of the 1997 European conference on Design and Test
MUSTC-Testing: Multi-Stage-Combinational Test scheduling at the Register-Transfer Level
VLSID '95 Proceedings of the 8th International Conference on VLSI Design
15.2 Low Cost Partial Scan Design: A High Level Synthesis Approach
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
SymSim: Symbolic Fault Simulation of Data- ow Data-path Designs at the Register-Transfer Level
ITC '99 Proceedings of the 1999 IEEE International Test Conference
ITC '99 Proceedings of the 1999 IEEE International Test Conference
A New Testability Calculation Method to Guide RTL Test Generation
Journal of Electronic Testing: Theory and Applications
A parameterized graph-based framework for high-level test synthesis
Integration, the VLSI Journal
Co-evolutionary high-level test synthesis
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Transforming behavioral specifications to facilitate synthesis of testable designs
ITC'94 Proceedings of the 1994 international conference on Test
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