15.2 Low Cost Partial Scan Design: A High Level Synthesis Approach

Authors:
M. L. Flottes;R. Pires;B. Rouzeyre;L. Volpe
Affiliations:
-;-;-;-
Venue:
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Year:
1998

Citing 8
Cited 1

Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments

DAC '93 Proceedings of the 30th international Design Automation Conference
Data path synthesis

Integration, the VLSI Journal
Enhancing high-level control-flow for improved testability

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
High-level synthesis for easy testability

EDTC '95 Proceedings of the 1995 European conference on Design and Test
Partial Scan High-Level Synthesis

EDTC '96 Proceedings of the 1996 European conference on Design and Test
Analyzing Testability from Behavioral to RT Level

EDTC '97 Proceedings of the 1997 European conference on Design and Test
Hybrid symbolic-explicit techniques for the graph coloring problem

EDTC '97 Proceedings of the 1997 European conference on Design and Test
Considering testability at behavioral level: use of transformations for partial scan cost minimization under timing and area constraints

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

High-level test synthesis with hierarchical test generation for delay-fault testability

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Quantified Score

Hi-index	0.00

Visualization

Abstract

In this paper, we present a High Level Synthesis method for partial scan designs. High level testability information are used to guide the synthesis process towards designs with a minimal number of scan registers. The maximal fault coverage is achievable for these designs. This method mainly leans on ad-hoc modifications of the register allocation process.