A Partial Scan Method for Sequential Circuits with Feedback
IEEE Transactions on Computers
Behavioral synthesis of highly testable data paths under the non-scan and partial scan environments
DAC '93 Proceedings of the 30th international Design Automation Conference
Splicer: a heuristic approach to connectivity binding
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
HAL: a multi-paradigm approach to automatic data path synthesis
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
The Synthesis Approach to Digital System Design
The Synthesis Approach to Digital System Design
Accessibility Analysis on Data Flow Graph: An Approach to Design for Testability
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
SYNTEST: A Method for High-Level SYNthesis with Self-TESTability
ICCD '91 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
High-level variable selection for partial-scan implementation
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
ICEBERG: an embedded in-circuit emulator synthesizer for microcontrollers
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
15.2 Low Cost Partial Scan Design: A High Level Synthesis Approach
VTS '98 Proceedings of the 16th IEEE VLSI Test Symposium
Using a software testing technique to identify registers for partial scan implementation
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
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Classical strategies in design for testability are applied at the gate-level, after the RT-logic synthesis process. New techniques covering test and synthesis (Test Synthesis) are appearing but their application is mainly oriented to gate level (commercial tools such as Synopsys). On the other hand, most high-level synthesis tools do not take into account the testability of the final architecture. This paper presents a high-level synthesis system which includes testability improvement among its goals. The aforementioned system generates loop free circuits and are, therefore, easily testable with partial scan techniques. In order to achieve this, a complete RT-level loop classification is made and the origin at the algorithmic level is analyzed in order to avoid loops during the synthesis process, not only in the data path but also in the controller. With the usual high-level synthesis benchmarks, the proposed system reaches 100% fault coverages with a smaller area than other high-level synthesis tools.